Posts Tagged ‘resources’
Wednesday, February 10th, 2016
 One of the reasons I like using UVM is its tendency toward an organized structure and uniformity. Some may find it annoying to adhere to such a strict format in UVM, but I think it’s a good way to keep the basics of UVM engrained in your brain. You always want a good foundation and development of strong fundamentals in any endeavor. Verification is no different and UVM hammers the fundamentals home.
UVM has a great structure and organization paradigm. I consider there to be two distinct and fundamental elements in the UVM structure: Components and Objects. Now this characterization isn’t strictly correct because uvm_components are extended from uvm_objects, but I think they are used in such a way that warrants the distinction. I consider it similar to the idea of trucks and cars. In my view, trucks are also cars, but it’s useful to note the difference.
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Tags: debugging, resources, systemverilog, training, uvm, verification
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Tuesday, December 15th, 2015
FPGA designers using VHDL have three choices: Stick with VHDL, switch to SystemVerilog, or.. use the best of both. This guest blog from Doug Perry, Senior Member Technical Staff at Doulos, outlines the pros and cons of each.
The latest crop of FPGA devices are enormous when compared to ASICs that were built not that long ago. Verifying these ASICs required detailed plans, multiple tools, and sometimes special languages. Verification was key because the cost of a respin was prohibitive. FPGA designers using VHDL have three choices: Stick with VHDL, switch to SystemVerilog, or.. use the best of both. This guest blog from Doug Perry, Senior Member Technical Staff at Doulos, outlines the pros and cons of each.
The same is not necessarily true of FPGAs because they can simply be re-programmed when an error is found. However the cost of finding the error in the lab can still be very expensive. This is related to the fact that the number of LUTs available in the device has skyrocketed, but the number of IO pins has not. Therefore getting visibility into the inner workings of the device from outside becomes much more difficult. Finding the source of an error therefore also becomes increasingly difficult. To counteract this problem, designers need to find errors before the device gets into the lab. To do this they need to adopt ASIC-like verification methodologies.
Tags: doug perry, doulos, FPGA, resources, systemverilog, uvm, verification, VHDL, Webinar
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Tuesday, October 27th, 2015
 Just in time for Halloween, Aldec has released a popular past webinar Don’t be Afraid of UVM for Hardware Designers on YouTube.
Designers are usually very busy doing their work and have little time left for experimentation with new methodologies. Unfortunately for them, official documentation of UVM (Universal Verification Methodology) was written by Verification Engineers for Verification Engineers, concentrating on high-level features and completely neglecting lower-level details such as connecting UVM testbench to your design.
Our webinar starts with solid review of SystemVerilog interfaces with special attention paid to Virtual Interfaces. Then it proceeds to Sequences and other Data Items, processed by Sequencers and fed to the design under test via Drivers. The role of Monitors and Scoreboards in analysis of results is explained. The presentation concludes with environment configuration and running test from the top-level module.
For the rest of this article, visit the Aldec Design and Verification Blog.
Tags: design, hardware, resources, systemverilog, uvm, verification, Webinar, YouTube
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Thursday, March 13th, 2014
 In James Bond movies, Agent 007 has some awesome gadgets but never listens to Q’s instruction on how to use them properly. I’ve often wondered what it would be like if Bond actually did learn about the various features of his tools and how to use them most efficiently.
Sure, that would probably eliminate all of the plot twists that make for a great movie, but when it comes to real life – I don’t care for plot twists. What about you? If you were a secret agent given these tools to keep you out of trouble or even save your life – would you take the time to learn about all of the features?
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Tags: advanced verification platform, Aldec, hdl code, image plots, plot feature, plot windows, polar, qam constellations, resources, Riviera-PRO, simulation, time-domain based results analysis, traditional waveforms, using plots for hdl debugging, vector, verification
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One of the reasons I like using UVM is its tendency toward an organized structure and uniformity. Some may find it annoying to adhere to such a strict format in UVM, but I think it’s a good way to keep the basics of UVM engrained in your brain. You always want a good foundation and development of strong fundamentals in any endeavor. Verification is no different and UVM hammers the fundamentals home.
