Archive for the ‘FPGA Design’ Category
Tuesday, April 6th, 2021
Tasked with finding life in the form of microorganisms, the rover Perseverance landed on Mars at about 04:00 EST on February 18, 2021. The rover has multiple sensors and cameras to collect as much data as possible and, due to the volume of live data being recorded and the long data transmission time from Mars to Earth, a powerful processing system is essential.
However, whereas early Mars rovers were equipped mainly with CPUs and ASICs as the processing units, FPGAs are taking on much of the workload in Perseverance. Let’s consider why that is the case.
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Tags: FPGA benefits in space, FPGA perseverance rover, FPGAs in Space, HES-DVM, Perseverance rover
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Monday, May 4th, 2020
 These days verification teams no longer question whether hardware assisted verification should be used in their projects. Rather, they ask at which stage they should start using it.
Contemporary System-on-Chip (SoC) designs are already sufficiently complex to make HDL simulation a bottleneck during verification, without even mentioning hardware-software co-verification or firmware and software testing. Thus, IC design emulation is an increasingly popular technique of verification with hardware-in-the-loop.
Recently, hardware assisted verification became much more affordable thanks to the availability of high capacity FPGAs (like Xilinx Virtex UltraScale US440) and their adoption for emulation by EDA vendors.
A good example of such an emulation platform is Aldec’s HES-DVM. It can accommodate designs over 300 Million ASIC gates on multi-FPGA boards (HES-US-1320), where the capacity scales by interconnecting multiple boards in a backplane.
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Tags: ARM, asic, embedded, Emulation, FPGA, HES-DVM, simulation, SoC, verification
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Wednesday, February 19th, 2020
Have you ever worked on a group project where you had to combine your work with that of a colleague of a different engineering discipline but the absence of an efficient means of doing so affected the project’s overall outcome? Well, for software and hardware engineers developing an SoC, the merging of their respective engineering efforts for verification purposes is a big challenge.
Early access to hardware-software co-verification allows hardware and software teams to work concurrently and set the foundation to a successful SoC project. However, many co-emulation methodologies are based on processor virtual models which are not accurate representations of the design. Fortunately, Aldec has a solution that integrates an ARM-based SoC from Xilinx, specifically a Zynq UltraScale+ MPSoC, with the largest Xilinx UltraScale FPGA. Since the Zynq device includes the hard IP of the ARM processor, our solution provides an accurate representation of the ARM-based SoC design for co-verification.
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Tags: ARM, asic, embedded, Emulation, FPGA, HES-DVM, SoC, SoC and ASIC Prototyping, Validation, verification, Zynq
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Monday, March 26th, 2018
 As an Applications Engineer I visit lots of potential customers, or talk to them at trade shows, who are doing FPGA designs but don’t own a commercial simulator. I ask them why that is. Most of the time it is budgetary restrictions. They don’t have funds to buy additional tools. I understand their situation and point out to them that at Aldec we have a very cost-effective simulator. But that is not what I want to talk about in this blog. I want to talk about engineers who say: “I am happy with the simulator my FPGA vendor provided me”, or “My simulations only take 15-20 minutes to run, I don’t think I need a faster simulator”, or “We don’t run simulations”.
That last response haunts me the most. For instance, at a recent site visit I was told: “We just load the design on our FPGA and test it out”. I asked how long does a full test iteration (i.e. program FPGA -> test -> debug -> re-code -> re-program) takes. They said about an hour or two, depending on the bug. I then asked how much of that time spent just running synthesis and programming the board? They said about 30 minutes.
Next, I proceeded to explain the benefits of running simulations in such scenario.
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Tags: debugging, design, FPGA Simulation, Riviera-PRO, simulation, verification
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Wednesday, February 28th, 2018
When should we use the term “Vision for Everything”, as vision-based applications are entering various industries? It’s been a few years since the emergence of Embedded Vision and we see that it’s being used in a wide range of applications including Security, Medical, Smart homes, Robotics, Transportations, Automotive Driver Assistance Systems (ADAS) and Augmented Reality (AR).
This is the first in a series of blogs explaining what you need to know to start designing Embedded Vision applications which can be used in ADAS, from choosing the right device and tools to demystifying the vision algorithms used in automotive applications and how to implement them into FPGAs.
ADAS consists of two main parts, vision and sensor fusion. Cameras used in a smart car can provide the information such as object detection, classification and tracking. However, they don’t provide the distance between the vehicle and obstacles needed to prevent a collision. To do that, sensors such as LIDAR or RADAR come to play.
In this series of blogs, we will mainly focus on the vision side of the ADAS; but will cover sensor fusion in the future. The main goal of this series of blogs is to give an in-depth knowledge of Aldec’s complete ADAS reference design which includes 360-Degree Surrounding View, Driver Drowsiness Detection and Smart-Rear View.
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Tags: acceleration, ARM, embedded, FPGA, hardware, verilog, VHDL, Xilinx
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Thursday, January 25th, 2018
 A high-performance router is an absolute must if you want to run a high-traffic network in which different devices need to transfer and receive data as fast as possible. A router with a powerful processor and sufficient local memory reduces data hiccups and minimizes message loading and buffering times. But is that enough?
Because of the huge amount of data that people now generate – combined with the wealth of communication protocols, such as Wi-Fi, Ethernet, USB, SFP, QSFP – high-performance, hardware re-programmable routers are becoming popular. That hardware re-programmability is being delivered through FPGAs, and utilizing one as the main ‘processor’ on the router makes it easy to add or modify desired modules such as encryption and compression.
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Tags: acceleration, design, digital, embedded, Emulation, FPGA, hardware, industrial, prototyping, SoC, SoC and ASIC Prototyping, Xilinx
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Wednesday, November 29th, 2017
 Data analysis is often a very time consuming process for a hardware design or verification engineer. We always end up using the waveform viewer which may not be very efficient in giving us a high-level overview of what we’re looking for. Data that is spread across a long simulation cycle is very hard to visualize on the waveform. Whenever I have to analyze a huge chunk of data, I always wonder what would be the best way to do it. It is often cumbersome to go through even a millisecond’s worth of waveform data to analyze the bigger picture. There are of course other tools that can take a VCD file and perform an analysis but that involves buying and learning to use an additional tool.
Sometimes it’s not feasible to invest time and money into new tools. So we always go back to our trusty waveform viewer to make sense of the results. But what if there is a better way of analyzing such data, especially if you are doing some kind of signal processing application and have a lot of data that you would rather view in a format other than the time domain based representation of a waveform? For example, imagine you are trying to visualize the data of an FFT engine. On a waveform, it is next to impossible to visualize this.
In Riviera-PRO we have the Plots feature which can help you. The plot window ties directly to the simulation database, so you don’t have to code anything new or learn a new tool. Just with a few clicks you can add objects to the plot viewer and, based on the settings, it will generate a plot of that object. Sounds very simple but it gives you a bigger picture of what your design object is doing over the course of the entire simulation, rather than just the slice you can see on the waveform between two points of time.
For the rest of this article, visit the Aldec Design and Verification Blog.
Tags: co-simulation, debugging, DSP, hardware, plots, processing, Riviera-PRO, signal, simulation, verification, waveform
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Tuesday, September 26th, 2017
 Well, summer has been and gone; and for most of us it was a time to relax and reflect on our working practices. What can we do to achieve better results? And what can we do to break out of the routine of working on so many revisions?
For me, one of my summer break ponderings was thinking back on a trick I learned while working with my colleagues at the Silesian University of Technology.
CMOS technology is the one that has dominated all applications of digital circuits. Power consumed by a CMOS digital circuit is the sum of two components: static power and dynamic power. The static power is a characteristic feature of the technology process used, and is associated with leakage currents in steady state. The dynamic power consumed by a CMOS gate is proportional to average switching activity at the output of the gate, which describes how often the state at the gate output is changing. The dynamic power component can thus be considered and minimized in the appropriate process of logic synthesis.
The essence of logic synthesis oriented toward energy-efficiency requires finding a circuit structure in which the number of state transitions is minimized.
Switching global clock networks are responsible for a significant part of the total power dissipated by a CMOS VLSI circuit. That’s why many engineers try to block the clock signal to achieve power reductions in synchronous circuits.
Programmable Logic Devices (PLDs), and especially Field Programmable Gate Arrays (FPGAs), constitute a relatively new and rapidly developing branch of digital electronics. Constantly growing logic capacities at moderate prices make PLDs an attractive platform for not only prototyping but also short- and medium-volume production.
It is not always obvious though how best to map logic structures (resources) within a given PLD architecture when designing with energy-efficiency in mind. In particular, implementing clock gating is difficult, as PLD circuits contain dedicated clock networks, which do not contain any gating elements. “Disabling” the clock signal in PLD structures can be accomplished in two ways: firstly, by utilizing the “Enable Clock” inputs of memory elements or, secondly, by distributing the clock signal using local clock lines or general-purpose routing resources (which enable the insertion of logic gates). For the rest of this article, visit the Aldec Design and Verification Blog.
Tags: FPGA, fsm, ICCMSE2017, Low-power, Riviera-PRO, university, verification
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Friday, August 25th, 2017
 The history of System-on-Chip (SoC)
Do we prefer to have a small electronic device or a larger one? The answer will often be “the smaller one”. However, before the commercialization of small radios, many people were interested in having big radios for the extravagance. Subsequently, at the beginning of the emergence of compact radios, those who preferred the flamboyance of large radios refused using compact radios. Slowly, but surely, the overwhelming benefits of owning a more compact radio led to the proliferation of smaller devices. These days the progression of the technology enables cutting-edge companies to encapsulate different parts of a system into increasingly smaller devices, all the way down to a single chip, which added the System-on-Chip (SoC) concept to the electronics world. By way of an example of a SoC, I will explain the Zynq-7000 all-programmable SoC. It consists of two hard processors, programmable logic (PL), ADC blocks and many other features all in one silicon chip.
Before the invention of the Zynq, processors were coupled with a Field Programmable Gate Array (FPGA) which made communication between the Programmable Logic (PL) and Processing System (PS) complicated. The Zynq architecture, as the latest generation of Xilix’s all-programmable System-on-Chip (SoC) families, combines a dual-core ARM Cortex-A9 with a traditional (FPGA). The interface between the different elements within the Zynq architecture is based on the Advanced eXtensible Interface (AXI) standard, which provides for high bandwidth and low latency connections.
Before implementing the ARM processor inside the Zynq device, users were using a soft core processor such as Xilinx’s Microblaze. The main advantage of using Microblaze was, and remains, the flexibility of the processor instances within a design. On the other hand, the inclusion of hard processor in Zynq delivers significant performance improvements. Also, by simplifying the system to a single chip, the overall cost and physical size of the device are reduced.
Zynq Design Flow
The design flow for the Zynq architecture has some steps in common with a regular FPGA. The first stage is to define the specifications and requirements of the system. Next, during the system design stage, the different tasks (functions) are assigned to implementation in either PL or PS which is called task partitioning. This stage is important because the performance of the overall system will depend on tasks/functions being assigned for implementation in the most appropriate technology: hardware or software. For the rest of this article, visit the Aldec Design and Verification Blog.
Tags: ARM, embedded, FPGA, hardware, SoC and ASIC Prototyping
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Friday, August 11th, 2017
 FPGA Design Verification Challenge
The FPGA design and verification “ecosystem” changes rapidly to keep pace with the fast growing size of FPGA devices. The largest Xilinx Virtex UltraSCALE chips provide 4.4 Million logic cells or using another metric 50 million equivalent gate count.
To enable efficient design process for Virtex-7 and newer UltraSCALE FPGAs, Xilinx provides software called Vivado Design Suite. Besides supporting a classical HDL design flow, it also provides system level design tools like IP Integrator, System Generator or even High Level Synthesis, that are very convenient for designing large and complex designs.
Verification has always taken a significant share of the project schedule with HDL simulation being the main stage of that process. With such big designs however, even the fastest simulators would spend hours in simulation tasks.
Simulation Acceleration with HES-DVM™
Aldec’s HES-DVM bridges this gap enabling accelerated simulation with the design running in the FPGA and the testbench in the simulator.
Aldec has been providing HES™ – Hardware Emulation Solutions since 2001. During that time the HES evolved to address the most sophisticated design requirements and fulfill customers’ requirements. Thus, simulation acceleration is only one example of how HES can be used with other applications being hybrid co-emulation, in circuit emulation, and physical prototyping.
With simulation acceleration the user can move any synthesizable module from simulator to the FPGA thus offload some processing from the HDL simulator. Typically, an entire design is implemented in HES board and the simulator only executes the testbench.
Figure 1: Signal-level simulation acceleration
The HES boards are seamlessly integrated with the simulator with PCI Express x8 physical connection to the host workstation. The HES-DVM provides co-simulation interfaces for Aldec’s Riviera-PRO and Active-HDL simulators but also for other 3rd party simulators. It can be used both in Linux and Windows operating systems with all required PCIe drivers and interfaces working out of the box.
The DVM tool automates the process of design compilation and implementation for HES boards. It generates all necessary scripts and configuration files to run simulation acceleration in a given HES board but also brings many useful debugging features. Despite running your design in FPGA hardware you can keep simulation level visibility with an RTL View of all internal probes.
Figure 2: Design setup flow for acceleration using DVM™
Acceleration Benchmark
MIG controller for DDR3, AXI interconnect, two AXI traffic generators and one AXI protocol checker as shown in the following diagram.How much acceleration can I achieve? This is always the first customer’s question and frankly there is no straight answer because the result depends on the complexity of both the design and the testbench. Usually a good estimation can be obtained from running simulation profiling and then applying Amdahl’s rule. However, the best way to verify acceleration potential is just to experiment with a typical design, so we have created a simple design of a memory sub-system using Xilinx Vivado Design environment. It contains MIG controller for DDR3, AXI interconnect, two AXI traffic generators and one AXI protocol checker as shown in the following diagram.
Figure 3: Diagram created for memory subsystem benchmarking
Benchmark Results
Workstation and software used for benchmarking:
Workstation:
CPU: Intel(R) Core(TM) i7-3770K CPU @ 3.50GHz
RAM: 32 GB
HES Board: HES7XV4000BP_REV2, contains 2x Virtex7 2000 FPGA
Software:
OS: Linux CentOS 6, x86_64
Simulator: Riviera-PRO 2017.02
Design env: Vivado 2016.4
Acceleration env: HES-DVM 2017.02
If you are interested in further details about this project, benchmark, and tools which can significantly accelerate your simulation you can view the following application note: https://www.aldec.com/en/support/resources/documentation/articles/1915
Tags: acceleration, co-simulation, FPGA, HES-DVM, simulation, SoC and ASIC Prototyping, verification, Xilinx
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