Archive for the ‘Emulation/Acceleration’ Category
Tuesday, April 6th, 2021
Tasked with finding life in the form of microorganisms, the rover Perseverance landed on Mars at about 04:00 EST on February 18, 2021. The rover has multiple sensors and cameras to collect as much data as possible and, due to the volume of live data being recorded and the long data transmission time from Mars to Earth, a powerful processing system is essential.
However, whereas early Mars rovers were equipped mainly with CPUs and ASICs as the processing units, FPGAs are taking on much of the workload in Perseverance. Let’s consider why that is the case.
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Tags: FPGA benefits in space, FPGA perseverance rover, FPGAs in Space, HES-DVM, Perseverance rover
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Tuesday, August 11th, 2020
 In the early days of digital design, all circuits were designed manually. You would draw K-map, optimize the logic and draw the schematics. If you remember, we all did many logic optimization exercises back in college. It was time consuming and very error prone. This works fine for designs with a few hundred gates, but as the designs get larger and larger this became non-feasible.
Designs that are described at a higher level of abstraction are less prone to human errors. High-level descriptions of designs are done without significant concern regarding design constraints. The conversion from high-level descriptions to gates is done by using synthesis tools. These tools use various algorithms to optimize the design as a whole. This circumvents the problem with different designer styles for the different blocks in the design and sub-optimal design practices. Logic synthesis tools also allows for technology independent designs. Logic synthesis technology was commercialized around 2004, and since then it’s been part of the standard EDA tool chain for ASICs and FPGAs.
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Tags: acceleration, Active-HDL, design, embedded, Emulation, FPGA, FPGA Simulation, HDL, HES-DVM, Intel, Synthesis, systemverilog, verilog, Xilinx
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Tuesday, June 16th, 2020
 Everyday there are new devices appearing in homes, offices, hospitals, factories and thousands of other places that are part of the Internet-of-Things (IoT). Clearly, they need to be connected to the internet and there is a need for a huge amount of raw data to be collected , stored and processed on the cloud.
There are many data centers available to store the data. However, only some provide features specifically for IoT applications. One of the most complete cloud-based IoT services available is Amazon Web Services (AWS) IoT Greengrass. It enables edge devices to act locally on the data networked devices generate, and provides secure bi-directional communication between the IoT devices and the AWS cloud for management, analytics and storage.
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Tags: AWS, AWS IoT Greengrass, embedded, FPGA IoT, IoT Greengrass, Zynq development board, Zynq for IoT, Zynq SoC
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Monday, May 4th, 2020
 These days verification teams no longer question whether hardware assisted verification should be used in their projects. Rather, they ask at which stage they should start using it.
Contemporary System-on-Chip (SoC) designs are already sufficiently complex to make HDL simulation a bottleneck during verification, without even mentioning hardware-software co-verification or firmware and software testing. Thus, IC design emulation is an increasingly popular technique of verification with hardware-in-the-loop.
Recently, hardware assisted verification became much more affordable thanks to the availability of high capacity FPGAs (like Xilinx Virtex UltraScale US440) and their adoption for emulation by EDA vendors.
A good example of such an emulation platform is Aldec’s HES-DVM. It can accommodate designs over 300 Million ASIC gates on multi-FPGA boards (HES-US-1320), where the capacity scales by interconnecting multiple boards in a backplane.
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Tags: ARM, asic, embedded, Emulation, FPGA, HES-DVM, simulation, SoC, verification
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Tuesday, April 7th, 2020
 Achieving higher resolution is a never-ending race for camera, TV and display manufacturers. After the emergence of 4K ultra high definition (Ultra HD) imaging in the market, it became the main standard for today’s multimedia products. 4k Ultra HD brings us bigger screens which give an immersive feeling. With this standard, the pixilation problem was solved in the big screens. 4K consumers are everywhere, from live sport broadcasting to video conferencing on our mobile devices. There are, however, many technical challenges in developing systems to process 4k Ultra HD resolution data. As an example, a 4K frame size is 3840 x 2160 pixels (8.5 Mpixel) and is refreshed at a 60Hz, equating to about 500 Mpixel/sec. This requires a high-performance system to process 4k frames in real time. Another bottleneck is power consumption particularly for embedded devices where power is critical. Being low power yet high performance, FPGAs, have shown a strong potential to tackle these challenges. In this blog, you’ll learn all you need to know to start developing a 4K video conferencing project using FPGAs.
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Tags: 4K video Processing, embedded, FPGA Image Processing, FPGA Video Processing, Zynq MPSoC FPGA
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Wednesday, February 19th, 2020
Have you ever worked on a group project where you had to combine your work with that of a colleague of a different engineering discipline but the absence of an efficient means of doing so affected the project’s overall outcome? Well, for software and hardware engineers developing an SoC, the merging of their respective engineering efforts for verification purposes is a big challenge.
Early access to hardware-software co-verification allows hardware and software teams to work concurrently and set the foundation to a successful SoC project. However, many co-emulation methodologies are based on processor virtual models which are not accurate representations of the design. Fortunately, Aldec has a solution that integrates an ARM-based SoC from Xilinx, specifically a Zynq UltraScale+ MPSoC, with the largest Xilinx UltraScale FPGA. Since the Zynq device includes the hard IP of the ARM processor, our solution provides an accurate representation of the ARM-based SoC design for co-verification.
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Tags: ARM, asic, embedded, Emulation, FPGA, HES-DVM, SoC, SoC and ASIC Prototyping, Validation, verification, Zynq
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Monday, December 11th, 2017
Modern ASIC and SoC designs have increased in complexity such that multiple FPGAs of the largest capacity are now required to prototype the entire functionality of the design. As design sizes increase, more and more FPGAs are required. The capacity and pin limitations of FPGAs create constraints for how the ASIC/SoC design can be mapped into the FPGAs. Aldec’s HES-DVM’s prototyping mode accounts for the limitations of the target FPGAs and allows the user to map a design to the FPGAs within these constraints.
Partitioning a design to fit into multiple FPGAs can be a lot of work
Designing the partitions with HES-DVM is as easy as selecting specific VHDL/SystemVerilog design modules from the hierarchy and moving them to a desired partition. All information about the design modules and the amount of LUTs, Flip-flops, memory blocks, DSP slices, and I/O consumed are displayed for convenience. These values can also be viewed as a percentage of the target FPGAs’ available resources allowing you to know when an FPGA is full.
Adding a module to a partition
Mapping a partition to an FPGA
Once the partitions are finalized, each partition can be assigned to a specific FPGA. A design successfully fitting into the FPGAs on the target prototyping board is only the beginning. There still remains a big problem with the sheer number of connections between the partitions. Modern designs have thousands of internal signals interconnecting major blocks or sub-systems. It’s likely that there won’t be a sufficient amount of direct connections between FPGAs to support the design’s internal wiring. How can the large amount of internal design signals possibly be accommodated by the relatively smaller amount of I/O available from the FPGAs?
For the rest of this article, visit the Aldec Design and Verification Blog.
Tags: asic, FPGA, HES-7, HES-DVM, prototyping, SoC, SoC and ASIC Prototyping
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Wednesday, November 22nd, 2017
 For many years, emulators were available only to verification teams working on the largest projects in companies with deep enough pockets. Due to size rather than capabilities they were called “Big Box” emulators and typically were used in order to recover some of the time lost on RTL simulation. Meanwhile, FPGA technology has been available long enough to mature to the point where FPGA based emulation became available – and I’m not talking here about FPGA prototyping.
“Emulation – Prototyping, aren’t they just synonyms?”
Sure, they are not. The most significant differences between FPGA usage in prototypes and in emulation are shown in table 1.
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Prototyping
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Emulation
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Clock frequency
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10-200 MHz
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1-20 MHz
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Clock Topology
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Multiple asynchronous sources – limited number of domains
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Derived from emulation core clock – unlimited number of domains
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Speed Limitation
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Fixed,
Determined by Inter-FPGA signal multiplexing
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Adaptive,
Determined by FPGA-to-Host Comms, Inter-FPGA signal multiplexing
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Stimulus Source
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In-System, Real-world IO
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Host,
Connection with simulators, virtual platforms, virtual models and other testbenches
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Signal Capture
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Selected Nodes
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Full Visibility
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Memory Models
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Near-match to physical
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Modelled
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Design Setup
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Computer aided but with extensive user’s input and decisions
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Fully automated
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Table 1: Typical differences between FPGA usage in prototyping and emulation
FPGAs are the fastest platform for prototyping, but we can also harness that speed into our verification environment, then we can achieve runtime performance 2x to 5x faster than traditional “big box” emulation systems, and all at a fraction of the cost per gate per MHz.
“FPGAs are way too small for our SoC design, aren’t they?”
In the HES-US-2640 board, Aldec already has the largest capacity single FPGA boards commercially available today. Connecting 4 such boards in a backplane gives you 24 largest Xilinx UltraScale chips in which you can implement 633 Million ASIC Gates and still have 40% of capacity margin to facilitate FPGA Place & Route.
Figure 1: Scalable HES platform for prototyping & emulation
Not all designs need such excessive capacity, especially IoT projects, where the primary requirement is small footprint and energy-safe design. You will find the proper configuration in Aldec HES boards versatile portfolio containing Virtex-7, Virtex UltraScale and Kintex UltraScale based hardware.
For the rest of this article, visit the Aldec Design and Verification Blog.
Tags: Emulation, FPGA, hes-boards, prototyping
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Friday, August 11th, 2017
 FPGA Design Verification Challenge
The FPGA design and verification “ecosystem” changes rapidly to keep pace with the fast growing size of FPGA devices. The largest Xilinx Virtex UltraSCALE chips provide 4.4 Million logic cells or using another metric 50 million equivalent gate count.
To enable efficient design process for Virtex-7 and newer UltraSCALE FPGAs, Xilinx provides software called Vivado Design Suite. Besides supporting a classical HDL design flow, it also provides system level design tools like IP Integrator, System Generator or even High Level Synthesis, that are very convenient for designing large and complex designs.
Verification has always taken a significant share of the project schedule with HDL simulation being the main stage of that process. With such big designs however, even the fastest simulators would spend hours in simulation tasks.
Simulation Acceleration with HES-DVM™
Aldec’s HES-DVM bridges this gap enabling accelerated simulation with the design running in the FPGA and the testbench in the simulator.
Aldec has been providing HES™ – Hardware Emulation Solutions since 2001. During that time the HES evolved to address the most sophisticated design requirements and fulfill customers’ requirements. Thus, simulation acceleration is only one example of how HES can be used with other applications being hybrid co-emulation, in circuit emulation, and physical prototyping.
With simulation acceleration the user can move any synthesizable module from simulator to the FPGA thus offload some processing from the HDL simulator. Typically, an entire design is implemented in HES board and the simulator only executes the testbench.
Figure 1: Signal-level simulation acceleration
The HES boards are seamlessly integrated with the simulator with PCI Express x8 physical connection to the host workstation. The HES-DVM provides co-simulation interfaces for Aldec’s Riviera-PRO and Active-HDL simulators but also for other 3rd party simulators. It can be used both in Linux and Windows operating systems with all required PCIe drivers and interfaces working out of the box.
The DVM tool automates the process of design compilation and implementation for HES boards. It generates all necessary scripts and configuration files to run simulation acceleration in a given HES board but also brings many useful debugging features. Despite running your design in FPGA hardware you can keep simulation level visibility with an RTL View of all internal probes.
Figure 2: Design setup flow for acceleration using DVM™
Acceleration Benchmark
MIG controller for DDR3, AXI interconnect, two AXI traffic generators and one AXI protocol checker as shown in the following diagram.How much acceleration can I achieve? This is always the first customer’s question and frankly there is no straight answer because the result depends on the complexity of both the design and the testbench. Usually a good estimation can be obtained from running simulation profiling and then applying Amdahl’s rule. However, the best way to verify acceleration potential is just to experiment with a typical design, so we have created a simple design of a memory sub-system using Xilinx Vivado Design environment. It contains MIG controller for DDR3, AXI interconnect, two AXI traffic generators and one AXI protocol checker as shown in the following diagram.
Figure 3: Diagram created for memory subsystem benchmarking
Benchmark Results
Workstation and software used for benchmarking:
Workstation:
CPU: Intel(R) Core(TM) i7-3770K CPU @ 3.50GHz
RAM: 32 GB
HES Board: HES7XV4000BP_REV2, contains 2x Virtex7 2000 FPGA
Software:
OS: Linux CentOS 6, x86_64
Simulator: Riviera-PRO 2017.02
Design env: Vivado 2016.4
Acceleration env: HES-DVM 2017.02
If you are interested in further details about this project, benchmark, and tools which can significantly accelerate your simulation you can view the following application note: https://www.aldec.com/en/support/resources/documentation/articles/1915
Tags: acceleration, co-simulation, FPGA, HES-DVM, simulation, SoC and ASIC Prototyping, verification, Xilinx
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Thursday, June 15th, 2017
‘The cloud’ has been an industry buzz word for some time now and whilst the initial focus was on data storage and sharing – and spawned the likes of Dropbox – ‘cloud computing’ is currently the latest trend. For instance, Amazon’s cloud platform, Amazon Web Services (AWS), gives users access to servers and a range of applications. Storage is available as before but so too now are dedicated relational databases; which in Amazon’s case is provides through a different service.
Enterprise businesses are taking advantage of cloud computing platforms, and for a number reasons. These include pay-as-go (as opposed to investing considerable cap ex), speed and flexibility (resources and storage can be made available quickly), and one is spared the headache of maintaining a mass of IT hardware and keeping on top of software license renewals.
Also, earlier this year Amazon announced EC2 (Elastic Compute Cloud) F1, a compute instance with FPGAs that users can program to perform hardware accelerations. The F1 instance includes an FPGA developer Amazon Machine Image (AMI) which includes a development environment with scripts and tools for code compilation and design simulation.
It is expected the primary users of EC2 F1 will be software developers, working on complex and compute-intensive algorithms for which FPGAs lend themselves particularly well. For instance, High Performance Computing will increasingly exploit FPGA technology.
But let’s not forget one of the most important roles that FPGAs have been playing in our industry – EDA – for a number of decades: hardware acceleration for ASIC prototyping purposes.
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Tags: Active-HDL, Emulation, FPGA-based hardware emulation platform, hardware, Hardware Emulation, HES-DVM, mixed language simulations, SoC and ASIC Prototyping, system c, system verilog, utilise Virtex-7, verilog, VHDL, Virtex UltraScale FPGAs, Virtex-7
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