Archive for November, 2013
Monday, November 25th, 2013
 COMRATE™, the co-simulation solution developed by Aldec and Agilent is a lot like “couples-therapy” that can help get your digital blocks talking to the rest of your model-based design.
To illustrate, let’s take a look at a very basic model-level design and think about it from design-under-test perspective (i.e., what are the challenges associated with verifying this DUT):
For the rest of this article, visit the Aldec Design and Verification Blog.
Tags: agilent, Aldec, co-simulation, co-simulation flow, co-simulation solution, comrate, debugging, digital blocks, hdl models, mixed-signal, model-based design, multirate design, Riviera-PRO, system-level environment, system-level simulation, systemvue, verification, verification of multirate systems with multiple digital blocks
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Wednesday, November 20th, 2013
 As a DO-254 evangelist, I travel quite a bit attending conferences and meeting customers all over the world. One question I occasionally get from engineers is whether Aldec’s mil/aero verification solution, DO-254/CTS™, supports verification of FPGA designs with high speed interfaces (for example ARINC 818, LVDS, DDR3 or PCIe).
Depending where I’m at I’ll tell them, “Oui!” or “Hai!” or simply “You bet it does”. Occasionally I’ll respond, “화장실이 어디 있어요!” in hopes that someone will kindly direct me to the nearest restroom.
For the rest of this article, visit the Aldec Design and Verification Blog.
Tags: Aldec, arinc 818, arinc protocol for high bandwidth, aviation, avionics systems, c/c++ api, do-254, do-254/cts, FPGA, fpga designs, in-hardware verification results, low latency, mil/aero verification solution, safety-critical, uncompressed digital video transmission, waveform
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Wednesday, November 6th, 2013
 The recent ARM® TechCon Conference in Santa Clara was definitely the front-runner of my favorite conferences that I attended this year. Fun, informative and filled with software engineers, physical designers, design verification teams, and hardware engineers – ARM TechCon was the place to be to learn about the latest innovations from the embedded industry. Aldec was there showcasing our HES-DVM™ and HES-7™ platforms, which enable engineers to utilize emulation and FPGA-based prototyping to verify the latest ARM designs.
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Tags: Aldec, ARM, arm processors, arm techcon conference, arm-based processors, co-simulation, dual-core arm cortex-A9 processors, Emulation, hes-7 platforms, hes-7 soc db, HES-DVM, hw/sw verification platform, ICE, In-circuit emulation, prototyping, rtl simulation, SoC, SoC and ASIC Prototyping, Xilinx, xilinx zynq soc
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COMRATE™, the co-simulation solution developed by Aldec and Agilent is a lot like “couples-therapy” that can help get your digital blocks talking to the rest of your model-based design.
