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Posts Tagged ‘Verification’

Automating IP Design and Verification

Sunday, August 16th, 2020

In my last post, I mentioned the three products we announced at the virtual Design Automation Conference (DAC) this year: SoC Enterprise™ (SoC-E), Standard Library of IP Generators (SLIP-G™), and IDS NextGen™ (IDS-NG). I’ve already blogged in detail about SOC Enterprise, so for today I’m focusing on SLIP-G. This library is an extension to our product line that leverages our extensive experience in automating registers and sequences to provide more value for our customers.

It’s no surprise to anyone that design reuse plays a big role in today’s huge system-on-chip (SoC) projects. It’s impractical for any team to design and verify many millions of gates from scratch, so IP from different sources helps to make large SoCs feasible with smaller teams and accelerated schedules. Internal reuse from previous projects is almost universal, but over the past 25 years or so commercial IP has grown tremendously in value and importance. Instantiating a well-proven design block saves valuable time and resources while reducing verification effort.
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What ARE the Root Causes of Functional Flaws?

Thursday, November 1st, 2018

Functional flaws in our everyday electronics are annoying. Internet routers can suddenly stop working, or our smart phones can suddenly freeze. For safety-critical systems such as the airplane engine control system, functional flaws can be catastrophic, and can lead to fatalities of all passengers. For both consumer-type and safety-critical systems, ASIC/FPGA teams strive to minimize functional flaws to the best of their abilities using their verification prowess with the help of EDA tools.  The more the budget the better the resource they have for minimizing functional flaws.

I just attended the webinar about the results of the Wilson Research Group & Mentor’s 2018 Functional Verification Study, and I can say that I’m not surprised with the results regarding root causes of functional flaws – this is what my team and I come across with frequently when we talk to our prospective customers and verification community.

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Agnisys at DVCon Europe

Tuesday, October 23rd, 2018

Our team is headed to Munich for DVCon Europe this week and we hope to see you there.

DVCon Europe- Booth #305
Munich, Germany
October 24-25, 2018

Related Press Release
Agnisys at DVCON Europe 2018: Presenting End-to-End Solution for Specification to Design and Verification of the Hardware/Software Interface

Agnisys Inc., the leading EDA provider of the industry’s most comprehensive solution for Design and Verification of the Hardware/Software Interface (HSI), will present the latest release of IDesignSpec™ at DVCon Europe in Munich, Germany on October 24-25, 2018.

“The latest release of IDesignSpec includes several new features to address emerging challenges associated with HSI particularly for large SoC designs,” said Anupam Bakshi, CEO. “Our customers across the globe predominantly develop the newest and greatest SoCs in the market and their requirements continue to push our product capabilities towards unexplored territories – helping us innovate further.”

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The Current State of the Art of HSI – Live Webinar

Thursday, September 20th, 2018

UPDATE: This event has now passed.

If you missed it, please view the recorded version here: Hardware Software Interface (HSI) Specification and Productivity Improvement Recorded Webinar

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Join Agnisys for a free webinar on Thursday, September 27, 2018. I’ll be presenting as we take a deep dive into the current state of the art of HSI with a focus on the HSI layer in embedded systems.

The Hardware Software Interface is an integral part of any system development. Get this wrong and you can say adios to having a robust system. Get this right and say hello to productive teams and system development done right.

Register for a time that is convenient for you.

Hardware Software Interface (HSI) Specification and Productivity Improvement Webinar
Thursday, September 27, 2018
3:00 PM – 4:00 PM CEST OR 11:000 AM – 12:00 PM PDT

 

Shift Left: Verification and Validation are two sides of the same coin

Friday, April 27th, 2018

Verification-and-ValidationVerification and Validation are two sides of the same coin

In 2011, Intel discovered a design flaw in its Sandy Bridge combination graphics-microprocessor chip that led to not only a major production delay but that ultimately cost more than $1 billion in replacement costs and lost revenue. If you’re searching for a clear-cut example as to why finding bugs early in the development process is always a top priority, look no farther than that. A product recall can be a terrible experience for everyone involved, but the costs associated with that recall alone are the stuff that nightmares are made of.

Yet at the same time, the complexity of the modern SoC environment has made things difficult in this regard to say the least. Getting SoC to market (and doing so with quality) is such an enormous task that teams are always looking for newer and more innovative ways to shorten the development time. The situation has also raised the requirement to incorporate verification and validation as a one-step process to catch bugs from an early design stage. Bringing the enormous tasks of verification and validation closer together is great news for the entire semiconductor industry.

This, however, is where the concept of “shift left” enters the conversation. As its name suggests, “shift left” is a series of activities and processes that better position design teams to anticipate and address downstream issues upfront, thus fixing a small problem now before it becomes a much bigger (and more expensive one) tomorrow. It’s the heart of the idea that you should “test early and often.” It also does so in a way that has proven to shorten development times so that no time is wasted late in the process where every second counts.

Why This Matters

But before we can focus on the importance of “shift left,” we must first address the early stages of this process in general. Verification and Validation are two critical steps in the creation of electronic systems, but over the last few years, in particular, their roles (and how those roles relate to one another) has changed.

In the modern era, there is an urgent need to enable users to describe the programming and test sequences of a device in a way that automatically generates sequences ready to use from an early design and verification stage, all the way up through post-silicon validation.

For the rest of this article, please visit Agnisys.com.




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