Posts Tagged ‘SystemRDL’
Monday, July 19th, 2021
In my last post, I mentioned that Agnisys is currently in the middle of a series of new webinars on how specification automation benefits many teams developing intellectual property (IP) blocks and system-on-chip (SoC) designs. When we first started supporting register and memory automation, we focused on generating register-transfer-level (RTL) design descriptions and Universal Verification Methodology (UVM) simulation testbench models from executable specifications. You generate these outputs as soon as the specifications are ready and re-generate them every time that the specifications are updated throughout the project.
This is of clear benefit to design and verification engineers. The designers never have to write any RTL code for registers or memories, or update code manually when requirements change. Similarly, the verification team developing the UVM testbench for the IP or SoC incorporates the generated models without having to develop them by hand, and automatically updates them when needed. When we added sequence automation to our product family, we helped the UVM effort even more. Over time, we’ve added design and verification generation for a wide range of standards-based IP as well as SoC-level interconnection of IP and custom blocks.
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Tags: SemiEDA, SoC, SystemRDL, UVM
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Wednesday, June 23rd, 2021
If there’s one good thing to emerge amid all the challenges of the last year and a half, it’s improved technology for remote learning. On-line talks, webinars, and podcasts are nothing new, but with so many people working at home the importance of virtual options has grown. When was the last time you had a vendor physically visit your company in person to talk about a new tool or technology? When was the last time you attended an in-person conference or seminar? For many engineers, it has been well over a year since we were even in the office. We’ve relied on the web for just about everything.
At Agnisys, we’ve been doing regular webinars since well before the pandemic and they have been highly effective and successful. We offered a series last year that proved quite popular, and you may have noticed that we recently announced a new series that began a few weeks ago. With interest in remote learning at an all-time high, we fully expect a great turnout for all our upcoming virtual events. Even if you’ve attended some of our webinars before, I encourage you to check out our new series because we’re taking a dramatically different approach to the material.
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Tags: RTL, SoC, SystemRDL
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Tuesday, April 27th, 2021
It’s hard to think of any electronic design automation (EDA) innovation that’s had more impact than the Universal Verification Methodology (UVM). After decades of ad hoc designer-centric simulation and a few advanced verification teams using more automated methods, the UVM brought everyone involved in chip development into a new era. Verification engineers have ready access to object-oriented programming, constrained-random stimulus, self-checking tests, reusable models, functional coverage, assertions, and more. Both the UVM itself and the SystemVerilog language upon which it is built are industry standards, allowing teams to mix EDA tools from multiple vendors, and easily switch tools if they wish.
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Tags: RTL, SemiEDA, SoC design, SystemRDL, UVM RAL
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Friday, August 28th, 2020
Regular readers of this blog know that Agnisys started as the first company to fully automate the design, verification, and documentation of registers in chip designs. From a single specification, you can generate design RTL, UVM testbench models for simulation, and user documentation for the registers in your design. This saves your development teams weeks of time, especially when the design evolves and register changes can be propagated across the project with a specification update and the simple push of a button. IDesignSpec™ (IDS) remains our best-known and most widely adopted product.
We expanded our solutions to include the sequences to access and program your registers with ISequenceSpec™ (ISS). We automatically generate sequences for various types of register behavior, including access to individual fields within registers. This is highly valuable for your chip verification team. We also help your driver and firmware developers by generating C code to access and program the registers in the actual fabricated chip as well as in hardware-software co-simulation and emulation. Like IDS, ISS also generates documentation in several formats.
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Tags: SystemRDL
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