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Posts Tagged ‘IDesignSpec’

Automation of the UVM Register Abstraction Layer

Thursday, May 28th, 2020

A recent blog post noted that today’s RTL design verification (DV) environments are very powerful and very complex. The SystemVerilog-based Universal Verification Methodology (UVM) standard provides most of the key building blocks for the simulation testbenches at the heart of the DV process. The previous post focused on correct-by-construction of UVM testbenches using the DVinsight™ smart editor from Agnisys. This post shows how other solutions from Agnisys can automate the generation of the UVM Register Abstraction Layer (RAL) that provides testbench access to the registers and memories in the design being verified.

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Live Agnisys Webinar: Register Design – Tips and Tricks in IDesignSpec

Wednesday, September 11th, 2019

Agnisys invites you to join our Live Webinar:

Register Design – Tips and Tricks in IDesignSpec

Presented by: Nikita Gulliya, Agnisys R&D Engineer

IDesignSpec has become the de-facto solution for register design/verification. It has helped in the industry minimize SoC functional flaws that show up due to changes and errors in the functional specification by employing a golden specification methodology.

Register for a time that is convenient for you.

Thursday, September 19, 2019
3:00PM – 4:00PM CEST

Thursday, September 19, 2019
11:00AM – 12:00PM PDT

REGISTER NOW

IDesignSpec offers a wide-range of features and capabilities for various design use cases and strategies. As requested by many of our users, in this webinar, we will show you several design strategies and tips/tricks used by power-users of IDesignSpec.

We will cover:

  • Tool Overview
  • Tips and Tricks
    • Building a Hierarchical Specification
    • Customizing the generated RTL
    • Widely-used RTL Properties
    • Parameterization
    • Connecting custom RTL to the auto-generated register block
    • Creating a TCL as a top-level check for limiting access types, register types, field widths
    • Feature-based availability at block, register and field level
  • Q & A

Register Automation using Machine Learning

Tuesday, February 19th, 2019

By Louie De Luna, Agnisys Director of Sales and Marketing

Right after Google’s AlphaGo system defeated a human Go world champion in 2015, the hype of deep learning and machine learning (ML) was quickly assimilated into mainstream technology. In EDA, the application of ML algorithms actually dates back to 2008 – when two Machine Learning-related topics were presented at DAC. The first topic, Efficient System Design Space Exploration Using Machine Learning Techniques targeted design challenges and the second, Experiences and Advances in Formal and Dynamic Verification, targeted verification challenges.

As a company focused on solving both design and verification challenges associated to Hardware/Software Interface (HSI), Agnisys has extensive experience in register code generation and verification, so applying Machine Learning to register automation is a natural next step for us. Agnisys  register tool IDesignSpec is a fully-matured solution with a large user base, where it can generate register code directly from the specification in Word, Excel, IP-XACT or SystemRDL. But in an ideal world, our users would rather use plain and simple English text to describe the register behavior rather than use special properties and syntax. Natural, plain English is still the hallmark of specifications in today’s system design and a lot of useful and actionable information is embedded in the natural language specification text.

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What ARE the Root Causes of Functional Flaws?

Thursday, November 1st, 2018

Functional flaws in our everyday electronics are annoying. Internet routers can suddenly stop working, or our smart phones can suddenly freeze. For safety-critical systems such as the airplane engine control system, functional flaws can be catastrophic, and can lead to fatalities of all passengers. For both consumer-type and safety-critical systems, ASIC/FPGA teams strive to minimize functional flaws to the best of their abilities using their verification prowess with the help of EDA tools.  The more the budget the better the resource they have for minimizing functional flaws.

I just attended the webinar about the results of the Wilson Research Group & Mentor’s 2018 Functional Verification Study, and I can say that I’m not surprised with the results regarding root causes of functional flaws – this is what my team and I come across with frequently when we talk to our prospective customers and verification community.

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Agnisys at DVCon Europe

Tuesday, October 23rd, 2018

Our team is headed to Munich for DVCon Europe this week and we hope to see you there.

DVCon Europe- Booth #305
Munich, Germany
October 24-25, 2018

Related Press Release
Agnisys at DVCON Europe 2018: Presenting End-to-End Solution for Specification to Design and Verification of the Hardware/Software Interface

Agnisys Inc., the leading EDA provider of the industry’s most comprehensive solution for Design and Verification of the Hardware/Software Interface (HSI), will present the latest release of IDesignSpec™ at DVCon Europe in Munich, Germany on October 24-25, 2018.

“The latest release of IDesignSpec includes several new features to address emerging challenges associated with HSI particularly for large SoC designs,” said Anupam Bakshi, CEO. “Our customers across the globe predominantly develop the newest and greatest SoCs in the market and their requirements continue to push our product capabilities towards unexplored territories – helping us innovate further.”

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The Intersection of Functional Safety and Electronic Design – How Safe is Your Ride?

Sunday, May 27th, 2018

The-Intersection-of-Functional-SafetyThe Intersection of Functional Safety and Electronic Design

In an industry that has gone through an incredibly rapid transformation over the past few years alone, auto manufacturers all over the world have had to rethink nearly every aspect of their own processes within the context of the 21st century. Because of this, an almost incredible emphasis has been placed on what concepts like “functional safety” even mean in 2018 (or 2019, or 2020 and beyond). This is especially true as vehicles incorporate more and more electronics with each passing day.

Autonomous vehicles have elevated this concern to the next level because as the level of control that a driver has over their car goes down, the liability of that car’s manufacturer shoots sky high. Many studies have shown that when automated systems are introduced into an industry, there is often a significant increase in the rate of “adverse” events as a result. This is the point that we have currently reached in terms of self-driving cars and functional safety.

In an effort to mitigate this risk as much as possible, functional safety is necessary – but in a way that also addresses the needs of what is already a high-volume, cost-sensitive industry. Luckily, the tools to address this problem sooner rather than later are already here. They just require us to keep a few key things in mind.

Functional Safety in Automotive Electronics: Breaking It Down

One of the most important elements of functional safety as it relates to the embedded systems that are now present in modern day vehicles has to do with fault detection. Simply put, regardless of where a particular fault comes from, the system’s ability to both A) identify it, and B) resolve it in the minimum time span possible is and will always be the goal.

In a lot of ways, this requires functional safety to take a more proactive approach to its own objective than ever before. Especially in an era of self-driving and autonomous vehicles where drivers are relinquishing more control all the time, the system itself must become aware of that fault and, if possible, recover from it, all without either endangering the passengers or requiring any intervention on their behalf, to begin with.

For the rest of this article, please visit Agnisys.com.




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