Posts Tagged ‘hsi’
Sunday, March 31st, 2019
As generations of designs evolved from a few hundred transistors to hundreds of billions, our industry abstracted the problem space from transistors to schematics to gates, and from RTL bit-level to transaction-level. Using abstraction, designers were able to focus on the high-level design and tests while the tools took care of the automation and calculations at the low-level – this certainly made the design flow more efficient and engineers more productive. Over the years abstraction has allowed the EDA industry to manage the ever-increasing complexity and scale of ASIC/SoC designs.
On a related note, check out Mark Glasser’s blog regarding his perspective on abstraction(while your there check out his great photography too).
The strategy behind the Portable Test and Stimulus Standard (PSS) is again to raise this level of abstraction to the next level. PSS will enable SoC teams specify stimulus and tests at a high-level. PSS has constructs for modeling high-level test scenarios such as data flow (buffer, streams, states), behavior (actions, activities, components, resource, pooling), constraints, randomization and coverage. The PSS tool generates the downstream code reusable from block, subsystem and system-level, which can be re-targeted for various verification platforms such as simulation, emulation, prototyping or post-silicon validation.
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Tags: Agnisys, Assertions, Automation, functional verification, hsi, IDesignSpec, ISequenceSpec, ISS, PSS, UVM registers, Verification
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Tuesday, February 19th, 2019
By Louie De Luna, Agnisys Director of Sales and Marketing
Right after Google’s AlphaGo system defeated a human Go world champion in 2015, the hype of deep learning and machine learning (ML) was quickly assimilated into mainstream technology. In EDA, the application of ML algorithms actually dates back to 2008 – when two Machine Learning-related topics were presented at DAC. The first topic, Efficient System Design Space Exploration Using Machine Learning Techniques targeted design challenges and the second, Experiences and Advances in Formal and Dynamic Verification, targeted verification challenges.
As a company focused on solving both design and verification challenges associated to Hardware/Software Interface (HSI), Agnisys has extensive experience in register code generation and verification, so applying Machine Learning to register automation is a natural next step for us. Agnisys register tool IDesignSpec is a fully-matured solution with a large user base, where it can generate register code directly from the specification in Word, Excel, IP-XACT or SystemRDL. But in an ideal world, our users would rather use plain and simple English text to describe the register behavior rather than use special properties and syntax. Natural, plain English is still the hallmark of specifications in today’s system design and a lot of useful and actionable information is embedded in the natural language specification text.
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Tags: Agnisys, Automation, DVCon, Free register Generator, functional verification, hsi, IDesignSpec, Register Generator
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Thursday, November 1st, 2018
Functional flaws in our everyday electronics are annoying. Internet routers can suddenly stop working, or our smart phones can suddenly freeze. For safety-critical systems such as the airplane engine control system, functional flaws can be catastrophic, and can lead to fatalities of all passengers. For both consumer-type and safety-critical systems, ASIC/FPGA teams strive to minimize functional flaws to the best of their abilities using their verification prowess with the help of EDA tools. The more the budget the better the resource they have for minimizing functional flaws.
I just attended the webinar about the results of the Wilson Research Group & Mentor’s 2018 Functional Verification Study, and I can say that I’m not surprised with the results regarding root causes of functional flaws – this is what my team and I come across with frequently when we talk to our prospective customers and verification community.
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Tags: ASIC, DO-254, Embedded, FPGA, functional safety, Functional Verification, hsi, IDesignSpec, Specification, Verification
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Tuesday, October 23rd, 2018
Our team is headed to Munich for DVCon Europe this week and we hope to see you there.
DVCon Europe- Booth #305
Munich, Germany
October 24-25, 2018
Related Press Release
Agnisys at DVCON Europe 2018: Presenting End-to-End Solution for Specification to Design and Verification of the Hardware/Software Interface
Agnisys Inc., the leading EDA provider of the industry’s most comprehensive solution for Design and Verification of the Hardware/Software Interface (HSI), will present the latest release of IDesignSpec™ at DVCon Europe in Munich, Germany on October 24-25, 2018.
“The latest release of IDesignSpec includes several new features to address emerging challenges associated with HSI particularly for large SoC designs,” said Anupam Bakshi, CEO. “Our customers across the globe predominantly develop the newest and greatest SoCs in the market and their requirements continue to push our product capabilities towards unexplored territories – helping us innovate further.”
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Tags: DVCon, Embedded, hsi, IDesignSpec, SemiEDA, Verification
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Thursday, September 20th, 2018
UPDATE: This event has now passed.
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Join Agnisys for a free webinar on Thursday, September 27, 2018. I’ll be presenting as we take a deep dive into the current state of the art of HSI with a focus on the HSI layer in embedded systems.
The Hardware Software Interface is an integral part of any system development. Get this wrong and you can say adios to having a robust system. Get this right and say hello to productive teams and system development done right.
Register for a time that is convenient for you.
Tags: Embedded, hsi, IDS NextGen, Verification, webinar
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Monday, August 27th, 2018
 As we travel professionally, sometimes we tend to miss some of the scenery along the way. We can get a bit of tunnel vision as we busy ourselves with client meetings, conferences, socializing with potential new clients, and uncovering new ways to improve and expand ourselves globally.
My first official trip to Edinburgh snapped me out of that. Edinburgh, Scotland’s compact, hilly capital, is a magical place. From its medieval Old Town and elegant Georgian New Town with gardens, I couldn’t help but slow down and take the time to appreciate my surroundings.
As I slowed down, little details caught my eye. I marveled at the public transport – so connected, punctual, convenient, and cost-effective. Not to mention the jovial nature of the Scottish people and the greetings and smiles I received every morning from strangers.
Between meetings, I squeezed in a visit an ancient monument – the Edinburgh Castle, Scotland’s most-visited paid tourist attraction. The Scottish monuments were quite spectacular and intricately detailed.
It was interesting to read that at the time of second world war, the Crown Jewels were kept in the Castle under a toilet! Of course, I had to see them, they didn’t allow a picture of the original but here is a photo its brass replica.
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Tags: hsi, SemiEDA, stu sutherland, travel, webinar
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Wednesday, July 18th, 2018
 This was an intriguing DAC. Hardware-Software Interface (HSI) is increasingly emerging as an area of importance, and because of this Agnisys has begun to emerge as a must-have toolset in the system development toolchain.
It still surprises me that some are just now waking up to this critical area of design. Teams are realizing that the chain is only as strong as its weakest link, and a design is only as robust as the weakest automation script. They are replacing their internal scripts with off-the-shelf professional tools. Agnisys, I’m proud to say, provides just that – professional products to replace register automation scripts.
One thing I did hear many times from attendees is that they are no longer satisfied with just creating register models. They want a test suite that automatically verifies the IP/SoC registers using a variety of techniques including C, UVM, and Formal. We nearly ran out of brochures for ARV-Sim™, ARV-Formal™, and ISequenceSpec™, as these products are intentionally built for exactly that.
Functional Safety driven by the ISO 26262 standard continues to be another hot area. Designers are looking for certified tools that can help them create autonomous vehicles and embedded electronics for automobiles. We shared our solution that fits in the intersection of Functional Safety and Electronic Design.
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Tags: dac, functional safety, hsi, machine learning, SemiEDA
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