When engineers discuss system-on-chip (SoC) designs, they’re almost always talking about embedded systems with both hardware and software content. In fact, many argue that a chip must contain at least one embedded processor to qualify as an SoC. Embedded systems have many design and verification challenges, and these apply fully to SoCs. The silicon technology really doesn’t matter; embedded FPGA designs can be huge these days and every bit as complex as ASICs or full-custom chips. Tackling the development challenges for these systems requires an automated, unified flow that covers both hardware and software, spanning design, verification, software, and documentation.
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A Unified Development Flow for Embedded Systems
Friday, December 11th, 2020Enhance Your Design and Verification Knowledge with Extensive Webinar Series
Wednesday, April 8th, 2020There is no easier way to learn new material than with a webinar in the comfort of your own home or office. Webinars bring experts directly to you with the latest results from both research and practical experience. Live webinars offer immediacy and interaction, while recorded webinars offer the chance for many more participants to benefit from the material over time. At Agnisys, we have found that webinars are an excellent way to educate the industry on key design and verification challenges in IP/FPGA/ASIC development. With the current circumstances in the world and so many engineers working from home, all forms of online learning are more important than ever.
Automating Design Assembly
Tuesday, March 3rd, 2020The consumer revolution over the past few decades has funneled a growth of SoC chips primarily in the area of consumer electronics. This revolution along with the increase of automotive and industrial electronics has led to a trend in convergence of applications on a single device. Companies vying for a bigger share of the market place are enticing their consumers by offering new or better features, which often adds to design complexities. In this competitive food chain, chip design companies are tragetting the companies developing these consumer devices with a range of functionalities embedded in single chip solutions. This convergence in applications as well as the growth of new technologies such as IoT, augmented reality, AI etc. has resulted in increasing demands on design complexity and design performance. With an increase in design complexity and a reduction in time to market, chip designers are now grappling with ways to meet the performance requirements while at the same time reduce the design cycle.
Consequently, design teams are increasingly compelled to look at methodology changes that can help accelerate chip assembly through one or multiple forms of automation.
Setting the Stage for the Next Abstraction
Sunday, March 31st, 2019As generations of designs evolved from a few hundred transistors to hundreds of billions, our industry abstracted the problem space from transistors to schematics to gates, and from RTL bit-level to transaction-level. Using abstraction, designers were able to focus on the high-level design and tests while the tools took care of the automation and calculations at the low-level – this certainly made the design flow more efficient and engineers more productive. Over the years abstraction has allowed the EDA industry to manage the ever-increasing complexity and scale of ASIC/SoC designs.
On a related note, check out Mark Glasser’s blog regarding his perspective on abstraction(while your there check out his great photography too).
The strategy behind the Portable Test and Stimulus Standard (PSS) is again to raise this level of abstraction to the next level. PSS will enable SoC teams specify stimulus and tests at a high-level. PSS has constructs for modeling high-level test scenarios such as data flow (buffer, streams, states), behavior (actions, activities, components, resource, pooling), constraints, randomization and coverage. The PSS tool generates the downstream code reusable from block, subsystem and system-level, which can be re-targeted for various verification platforms such as simulation, emulation, prototyping or post-silicon validation.
Register Automation using Machine Learning
Tuesday, February 19th, 2019By Louie De Luna, Agnisys Director of Sales and Marketing
Right after Google’s AlphaGo system defeated a human Go world champion in 2015, the hype of deep learning and machine learning (ML) was quickly assimilated into mainstream technology. In EDA, the application of ML algorithms actually dates back to 2008 – when two Machine Learning-related topics were presented at DAC. The first topic, Efficient System Design Space Exploration Using Machine Learning Techniques targeted design challenges and the second, Experiences and Advances in Formal and Dynamic Verification, targeted verification challenges.
As a company focused on solving both design and verification challenges associated to Hardware/Software Interface (HSI), Agnisys has extensive experience in register code generation and verification, so applying Machine Learning to register automation is a natural next step for us. Agnisys register tool IDesignSpec is a fully-matured solution with a large user base, where it can generate register code directly from the specification in Word, Excel, IP-XACT or SystemRDL. But in an ideal world, our users would rather use plain and simple English text to describe the register behavior rather than use special properties and syntax. Natural, plain English is still the hallmark of specifications in today’s system design and a lot of useful and actionable information is embedded in the natural language specification text.
