A Unified Flow for Embedded Systems Development

Over the last couple of months, I have discussed some key recent additions to the Agnisys solutions for system-on-chip (SoC) automation, including three new products announced at this year’s virtual Design Automation Conference (DAC). These innovations continue our history of building upon our expertise in the automation of register design and verification to encompass many other aspects of embedded systems development. We provide real value to your architects, designers, verification engineers, software developers, technical writers, and chip testers.

The key idea that links all our products and solutions is using an executable specification as the single source of information across all your project teams. From a single specification, you can generate design RTL, complex programming and test sequences, UVM testbench models for simulation, portable stimulus standard (PSS) models, assertions for formal verification, C code for firmware and device driver development, CSV files for automatic test equipment (ATE), and end-user documentation in multiple formats.

No duplication of information means no wasted time, money, or resources and no chance for multiple representations to get out of sync as the project evolves. Changes to the specification require only the push of a button to update all generated files. We support a wide range of specification formats, including industry standards such as IP-XACT and SystemRDL, popular tools such as Microsoft Word and Excel, and our own specialized editors. We generate output files in dozens of different formats to support the diverse users in your teams.

We first implemented this approach for control and status registers (CSRs) and over the last few years we have extended it in several directions. As a quick summary, here is the range of our current products:

• IDesignSpec™ (IDS) automates design, verification, and documentation of your CSRs
• Specta-AV™ generates a comprehensive UVM testbench and test sequences
• ASVV™ generates device driver building blocks and supports bare-metal verification
• SoC Enterprise™ (SoC-E) assembles a complete SoC from IP and your design blocks
• Standard Library of IP Generators (SLIP-G™) is a set of configurable IP generators
• DVinsight™ is a smart editor for creating UVM-based SystemVerilog code

Clearly, we have come a long way from being a single-product company focused solely on register design. In many ways, the products introduced this year deliver on our longtime vision for a complete, fully automated, specification-based solution for registers and sequences from specification to assembly, design, verification, and validation of complex SoC devices. But it takes more than products to provide a complete solution; a methodology-based flow is also needed. We have worked with our leading users to develop and validate such a flow and will be presenting it in an upcoming webinar.

We invite you to join us for “System Development Using Agnisys: The fastest path to an embedded system from specification” to fill in all the details. This event is being held at the following time:

• 30 October, 10:00 AM-11:00 AM KST (Korea)
• 29 October, 6:00 PM-7:00 PM PST (USA)
• 30 October, 06:30 AM-07:30 AM IST (India)

If this time is not convenient for your location, note that a recorded version of the webinar will be available for later viewing. You can learn more and sign up here. I sincerely hope that you will be able to join us to see the full scope of value that we can bring to your most complex SoC-based embedded systems projects.

This entry was posted on Wednesday, October 28th, 2020 at 5:23 am. You can follow any responses to this entry through the RSS 2.0 feed. You can leave a response, or trackback from your own site.