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 Agnisys Automation Review

Archive for September, 2020

AI-Based Sequence Detection for IP and SoC Verification and Validation

Monday, September 28th, 2020

A couple of years ago at the Design Automation Conference (DAC), as I walked the exhibit floor I was amused by how many EDA vendors had jumped on the marketing bandwagon for artificial intelligence (AI) and machine learning (ML). Many company slogans, booth posters, and demonstrations claimed that AI/ML techniques had been incorporated into their products. Doubtless some of these claims were true, but for certain companies and product categories it was hard to believe. In this post, I’ll discuss a real use of AI/ML technology at Agnisys, already implemented and available to users now.

Let’s start by defining a few terms. AI is a broad description referring to any computer program that automatically does something that would traditionally have required human intelligence. AI works at its best by combining large amounts of data with fast, iterative processing and intelligent algorithms. ML is a subset of AI using advanced techniques and models that enable computers to figure out interesting things from the datasets and deliver AI applications. Along with the algorithms, what is most important for AI/ML is the quality and quantity of the data used to train the model for these algorithms.

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Specification-Driven UVM Testbench Generation

Tuesday, September 22nd, 2020

In February, we will celebrate the tenth anniversary of Accellera approving the first version of the Universal Verification Methodology (UVM). It’s no exaggeration to say that UVM changed the world of semiconductor verification. It wasn’t the first verification methodology, and not even the first to use SystemVerilog, but it was developed and supported by all major electronic design automation (EDA) vendors. Users could write testbenches using the UVM building-block library and its detailed guidelines, secure in the knowledge that simulators and other tools would handle them properly.

UVM focused the diverse set of constructs and powerful capabilities available in SystemVerilog on the specific task of building a reusable verification environment. Object-oriented programming (OOP) support meant that users could extend the building blocks without modifying them. Adherence to the guidelines made verification components reusable “horizontally” across projects and even across companies. Passive components such as monitors and coverage collectors, and even some active interface models, could be reused “vertically” from block to subsystem to system.

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