AI-Based Sequence Detection for IP and SoC Verification and Validation

A couple of years ago at the Design Automation Conference (DAC), as I walked the exhibit floor I was amused by how many EDA vendors had jumped on the marketing bandwagon for artificial intelligence (AI) and machine learning (ML). Many company slogans, booth posters, and demonstrations claimed that AI/ML techniques had been incorporated into their products. Doubtless some of these claims were true, but for certain companies and product categories it was hard to believe. In this post, I’ll discuss a real use of AI/ML technology at Agnisys, already implemented and available to users now.

Let’s start by defining a few terms. AI is a broad description referring to any computer program that automatically does something that would traditionally have required human intelligence. AI works at its best by combining large amounts of data with fast, iterative processing and intelligent algorithms. ML is a subset of AI using advanced techniques and models that enable computers to figure out interesting things from the datasets and deliver AI applications. Along with the algorithms, what is most important for AI/ML is the quality and quantity of the data used to train the model for these algorithms.

One classic field using AI is natural language processing (NLP). Machine translation, speech recognition, conversational chatbots, and POS (parts of speech) tagging have been among the most popular NLP applications. NLP can be used for the development of deep learning (DL) models for classification of text, translation of text, and more. DL is a subfield of ML that focuses on the algorithms inspired by the structure and function of the brain. These techniques have proved useful in solving challenging NLP problems.

NLP is highly appropriate for EDA because natural language remains the most common format for IP and chip specifications. There are many academic methods for capturing specifications in executable format, and in certain areas such as assertions their use has become mainstream. However, many users would prefer to use plain and simple English text to describe their design and its features. One promising line of research has been the use of AI/ML/DL/NLP to convert natural language specifications into executable formats automatically.

At Agnisys, we have successfully applied AI techniques to process sequence descriptions written in natural language. Sequences are lists of steps that must be executed in order (flowcharts or algorithms) and are a key part of any design specification. They are used for verification (SystemVerilog/UVM) and for embedded code, IP/chip configuration, and backend testing and validation (C/C++). Sequences contain reads and writes to registers and fields, manipulate the pins of the design, wait for events, and call functions and subsequences.

The key to our technology is auto-sequence detection, in which our AI algorithms analyze sequences specified in natural language and generate the executable formats, including SystemVerilog/UVM and C/C++. We process all the words one by one and generate the output information as our result. We employ a bidirectional layer, which reads the input text from both the forward and backward directions. This improves the performance of the model on sequence classification. Our algorithms are tuned to predict the most probable expected output sequences from the text specification.

In any AI/ML application, the data that is fed to the model for training should be as good as possible. The dataset (corpus) must be appropriate to produce better performance from the model. We have carefully created our corpus by obtaining actual register programming sequences from industry and introducing a wide variety of cases including cases with augmented data and noise. This has yielded a robust model with high accuracy, covering almost all scenarios of sequences that can be described in a text specification.

We have auto-sequence detection available now in our recently announced IDS NextGen™ (IDS-NG) solution. It could not be easier for users to:

• Create their IP specification
• Click the “Check” button to detect any specification errors
• Select the sequence template and specify sequences in natural language (English)
• Review the sequence steps interpreted by NLP
• Select the desired output files
• Click on the “Generate” button to produce the outputs using those sequence steps

The following table shows just a few examples of natural language sequence description and the sequence steps generated by NLP.

We are pleased with the results of our current solution and have applied it on a wide variety of real-world test cases. We have been able to handle these cases with an accuracy of more than 90% with no delay in inference time. Our model can effectively handle noise in the input text and thus pay attention to only the relevant parts of the text that have an influence on generating correct output sequences. This approach scales from individual IP blocks to complete system-on-chip (SoC) devices. We offer cloud support in IDS-NG to access greater compute resources for large designs.

We always operate in a mode of continual improvement, especially important for NLP. One of the hallmarks of AI in general, and ML/DL in particular, is that applications are never truly “done.” Learning continues on an ongoing basis and the training dataset grows ever larger, leading to ever greater accuracy and robustness. Over time we will be able to recognize more words, handle unknown words more cleverly, provide better guidance when the text specification is insufficient, and handle more hierarchal and complex sequence scenarios.

The history of Agnisys has been all about automation of design and verification, including registers, sequences, testbenches, embedded code, and SoC assembly. With auto-sequence detection, we have taken a step further by helping users capture verification and validation sequences in natural language and by automatically generating output formats. This saves a great deal of time in UVM and C/C++ coding, both initially and as the design and sequences evolve, and ensures a consistent view of sequences across project teams. To learn more, please view our recent webinar.

Tags: SoC, testbenches

This entry was posted on Monday, September 28th, 2020 at 11:53 pm. You can follow any responses to this entry through the RSS 2.0 feed. You can leave a response, or trackback from your own site.