Open side-bar Menu
 Agnisys Automation Review

Archive for August, 2020

The Next Generation of Register, Sequence, and SoC Automation

Friday, August 28th, 2020

Regular readers of this blog know that Agnisys started as the first company to fully automate the design, verification, and documentation of registers in chip designs. From a single specification, you can generate design RTL, UVM testbench models for simulation, and user documentation for the registers in your design. This saves your development teams weeks of time, especially when the design evolves and register changes can be propagated across the project with a specification update and the simple push of a button. IDesignSpec™ (IDS) remains our best-known and most widely adopted product.

We expanded our solutions to include the sequences to access and program your registers with ISequenceSpec™ (ISS). We automatically generate sequences for various types of register behavior, including access to individual fields within registers. This is highly valuable for your chip verification team. We also help your driver and firmware developers by generating C code to access and program the registers in the actual fabricated chip as well as in hardware-software co-simulation and emulation. Like IDS, ISS also generates documentation in several formats.

Automating IP Design and Verification

Sunday, August 16th, 2020

In my last post, I mentioned the three products we announced at the virtual Design Automation Conference (DAC) this year: SoC Enterprise™ (SoC-E), Standard Library of IP Generators (SLIP-G™), and IDS NextGen™ (IDS-NG). I’ve already blogged in detail about SOC Enterprise, so for today I’m focusing on SLIP-G. This library is an extension to our product line that leverages our extensive experience in automating registers and sequences to provide more value for our customers.

It’s no surprise to anyone that design reuse plays a big role in today’s huge system-on-chip (SoC) projects. It’s impractical for any team to design and verify many millions of gates from scratch, so IP from different sources helps to make large SoCs feasible with smaller teams and accelerated schedules. Internal reuse from previous projects is almost universal, but over the past 25 years or so commercial IP has grown tremendously in value and importance. Instantiating a well-proven design block saves valuable time and resources while reducing verification effort.

A Quick Look Back at a Virtual DAC

Tuesday, August 4th, 2020

In my last blog post, I talked a bit about the history of the annual Design Automation Conference (DAC) and mentioned that this year it would be a virtual event due to the ongoing pandemic. The show concluded about ten days ago and so we’ve now had time to assess the results. I thought that some of you who were unable to attend might be curious how it went, so I’d like to provide a quick summary.

The first thing to say is that virtual events are still novel and a bit daunting for both exhibitors and attendees. This was the first virtual show for Agnisys, so it took some adjustment to our usual preparation and promotional efforts. The good news is that we had an impressive number of visitors to our DAC virtual booth, so lots of you were able to find out about us, our products, and our customers. We also had a quiz that proved quite popular. The less-good news is that some visitors didn’t navigate to the deeper engagement options. It seemed that the concept of the virtual booth was unclear, plus many users (including our own engineers) were stymied by technical issues on the DAC site.

© 2022 Internet Business Systems, Inc.
670 Aberdeen Way, Milpitas, CA 95035
+1 (408) 882-6554 — Contact Us, or visit our other sites:
TechJobsCafe - Technical Jobs and Resumes EDACafe - Electronic Design Automation GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise