A Quick Look Back at a Virtual DAC

In my last blog post, I talked a bit about the history of the annual Design Automation Conference (DAC) and mentioned that this year it would be a virtual event due to the ongoing pandemic. The show concluded about ten days ago and so we’ve now had time to assess the results. I thought that some of you who were unable to attend might be curious how it went, so I’d like to provide a quick summary.

The first thing to say is that virtual events are still novel and a bit daunting for both exhibitors and attendees. This was the first virtual show for Agnisys, so it took some adjustment to our usual preparation and promotional efforts. The good news is that we had an impressive number of visitors to our DAC virtual booth, so lots of you were able to find out about us, our products, and our customers. We also had a quiz that proved quite popular. The less-good news is that some visitors didn’t navigate to the deeper engagement options. It seemed that the concept of the virtual booth was unclear, plus many users (including our own engineers) were stymied by technical issues on the DAC site.

DAC is always a central event in the EDA industry, with many companies making major announcements aligned with the show. Going virtual didn’t change that; we made our most significant new product announcement in some time:

• Standard Library of IP Generators (SLIP-G™) provides an interface for IP customization and configuration, generating design RTL, UVM testbench models, and programming sequences. We have GPIO, I2C, timer, and programmable interrupt controller (PIC) IP available today.
• SoC Enterprise™ (SoC-E) is a flexible and customizable environment for design assembly. It can generate RTL aggregators, bridges, and multiplexors. Its Smart Assembler technology automatically connects these blocks, SLIP-G IP, other IP, and user blocks into a complete SoC.
• IDS NextGen™ (IDS-NG) ™ is a specialized integrated development environment (IDE) for large IP blocks and SoCs. It includes a sophisticated GUI for capturing register and sequence specifications, and provides a common front end for IDS, ARV, ISS, and SoC-E.

Of course, we are excited about these new solutions and we were delighted to share them as part of the information in our DAC virtual booth. We’re also excited to share three brand-new videos of customers explaining how Agnisys and our products improve their design and verification flows. Hands-on engineers from Allegro MicroSystems, Analog Inference, and Yellowbrick Data are developing very complex chips for fascinating applications, and I’m certain that you will enjoy their stories.

If you missed DAC or would like to take another look, the three videos and much more are still available in our virtual booth until September 1. After then, you can find the videos on our YouTube channel. We will see you soon online!

Tags: Allegro MicroSystems, Analog Inference, ARV, dac, IDS, ISS, SLIP-G, SoC, SoC-E, Yellowbrick

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