Adopting New Methods For Faster Development Of RISC-V based SoCs

The growth of new technologies such as artificial intelligence, machine learning, Internet of Things (IoT), virtual/augmented reality and of course, the various technologies for the automotive industry has led to a new surge in the development of semiconductor chips. The growth had been stunted in part due to the considerable cost involved in using the processor core, which forms the heart of most SoCs. The enormous cost, risk, development time and necessary volumes of developing a processor, has kept this lucrative industry in the hands of just a few companies. That is, until now.

With the development of the open source RISC-V ISA from UC Berkeley labs, based on the new computing needs in various power and performance dimensions, the semiconductor industry is once again at the cusp of embracing an incredible surge in innovation. Over the last few years, the interest in RISC-V has been gaining steam with commercial implementations and adoption growing rapidly.

The RISC-V core is an open development model that is managed by the RISC-V Foundation, which has a number of member companies. In a short span of time, it has helped foster an industry-wide collaboration, including building an ecosystem to work around it, especially since it is designed to support both proprietary and open implementations. With support for a variety of bus fabric such as TileLink and AMBA® AXI/AHB/APB, the RISC-V core becomes an ideal candidate for new applications such as wearable’s, high performance embedded systems such as smart IoT, AI etc.

But in the world we live in today, with increasing global competition, it becomes imperative to execute and deliver the SoCs or the IPs to satisfy the market need before others do. To capitalize on the evolving RISC-V ecosystem and opportunities the RISC-V core provides, many companies are leveraging new methods to shorten the development cycle.

One such method of speeding up the development is to create a singular golden specification for registers to be leveraged by different groups such as hardware, firmware, software, verification and validation groups. With automatic generation of verified RTL, C headers etc., the different groups are able to reduce the development cycle as well as mitigate the risk of silicon failure. This becomes very pertinent in the case of RISC-V as it differs from some of the other more established proprietary instruction sets by allowing, and in fact, encouraging, custom extensions to the instruction sets. The notion of creating a golden specification and generating the desired output format to aid in development, verification and validation is also gaining traction in the automotive industry, which is largely governed by the ISO 26262 standard. This method mitigates the risk of errors being inserted into the SoC/IP being developed thereby improving the reliability of the device.

With a complex processor core such as the RISC-V, a more robust hardware verification approach becomes necessary in order to ascertain the correct functionality. In fact to some extent it becomes mandatory to develop the necessary test scenarios and test environments for simulation, firmware tests and board testing. To create the desired stimulus, one would typically need UVM sequences for UVM-based simulation, C-based sequences for firmware and hardware/board tests.

One of the main challenges in creating the sequences is that multiple engineers with varying levels of expertise would need to write them in the target language for simulation, firmware tests and board testing, even though the functionality of the sequences remains the same. And before they can even code the sequences, they must first understand the test specification, which in itself requires a significant amount of time and effort. This causes a delay in the development and verification cycle, which the design teams can ill afford.

At the upcoming RISC-V summit, Agnisys will demonstrate solutions for the above-mentioned problems. This approach enables design teams to reduce their development and verification cycles for RISC-V based IPs/SoCs targeting both ASICs and FPGAs. We will also showcase how teams can automate their test environments for simulation, firmware development, emulation and post-silicon validation by creating standard and custom test sequences.

At the summit we will also demonstrate the following:
• Automatic detection of sequences from natural language.
• Automatic generation of virtual prototype models from the specification.
• Agnisys standard IP library with GPIO, Timer, I2C, PIC, DMA, etc. to help speed design development cycles.

For more information, stop by the Agnisys booth (#113) at the RISC-V summit next week from December 10-12 at the San Jose convention center.

Tags: IoT, RISC, RISC-V, RTL, SoCs, UVM

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