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 Agnisys Automation Review

Archive for January, 2020

Modeling And Verifying Hardware-Software Interface Manual Or Automatic

Wednesday, January 29th, 2020

System and chip design companies are always pushing the envelope to innovate while striving to shorten the development cycles, lower costs and mitigate the tape-out risks. It has now become more important than ever to have the flexibility to morph products quickly to meet the changing trends and yet meet tight time-to-market deadlines. The need to have this flexibility to meet the changing needs, has led design teams to develop a superset of features and modes which can be programmed to create desired variants of SoC’s and IPs.

The growth in areas such as AI, machine learning, virtual/augmented reality and automotive has also increased this need to have the flexibility to program the SoC in different modes and turn on/off the features as needed. This is more so in the case of evolving technologies where developers want to modify the settings of the SoC if needed.  The need for this flexibility has led to much of the functionality in a SoC-based system to be implemented as software leveraging the SoC platform to create the desired upgrades and variants of the chip.

The dual needs for increased productivity and flexibility are typically met by managing the hardware-software interface (HSI) effectively. Writing/reading registers and interrupts are the primary way that the behavior of most SoCs/IPs are controlled and queried. Modeling tens of thousands of registers manually and verifying them is an error prone task and inevitably leads to delays in project timelines, which design teams can ill afford. For the HSI to be successfully implemented, there is a need for interaction between system architects, software developers, hardware designers, system integrators and verification specialists, which is often at best tardy. This has led to a need for developing the HSI specification at higher levels of abstraction to define the different types of registers, memory maps, which can automatically generate an “executable”, such as Verilog, VHDL languages, C header files to be leveraged by all the stakeholders involved in the development of the SoC.


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