The complex SoCs of today typically contain thousands of registers, which are used to control the operations of the SoC/IP. The register specification, which is at the epicenter of a SoC/IP design is accessed by different teams such as hardware, software, verification and embedded design teams, all of which need to access the same source. A mismatch and misinterpretation of the specification simply results in un-necessary delays to the development cycle.
While there are several methods to define the register specification, such as Excel, Word, IP-XACT etc., SystemRDL is gaining popularity, as it is an easy-to-use textual language used for the design and delivery of SoCs/IPs. Released by Accellera, SystemRDL supports the complete project cycle of registers from the specification, model generation, and design verification to maintenance and documentation. It mitigates the problems encountered in describing and managing registers. SystemRDL enables a system architect or a hardware designer to create a functional specification of the hardware-software interface (HSI) for an SoC/IP, which can include addressable registers, interrupts, counters etc. This specification is then used by other members of the team including software, hardware and design verification to create representations of data in the languages they use in their aspect of the SoC development process.
