Agnisys Automation Review Louie De Luna
Louie is the Director of Marketing and Sales at Agnisys, Inc. He has over 15 years of experience in FPGAs, ASICs and EDA industries. Louie was most recently the Director of Marketing for Aldec where he was instrumental in the development and execution of the strategy for the entire functional verification solutions. He received his B.S. in Computer Engineering from University of Las Vegas, NV in 2001. « Less Louie De Luna
Louie is the Director of Marketing and Sales at Agnisys, Inc. He has over 15 years of experience in FPGAs, ASICs and EDA industries. Louie was most recently the Director of Marketing for Aldec where he was instrumental in the development and execution of the strategy for the entire functional … More » Automating Register Verification with 100% Functional CoverageDecember 4th, 2018 by Louie De Luna
UVM has certainly improved reusability of verification environments for SoC projects, significantly lowering the verification costs throughout the electronics industry. Since Accellera’s release in 2011, UVM is now an IEEE standard published as IEEE 1800.2-2017 – IEEE Standard for Universal Verification Methodology Language Reference Manual.UVM has definitely gone a long way. The UVM Register Layer classes have been quite useful for modeling memory-mapped registers and external memories in a DUT in which users are able to abstract the verification environment and standard tests from block to system level seamlessly with only minimum modifications. However, today’s average electronics consumer demand new use cases at ever-increasing speed and bandwidth – which certainly challenges SoC architects, designers and verification engineers, requiring them to be more creative in the implementation and modeling of the hardware/software interface (HSI). Modeling special registers is needed in order to meet special register behavior, which includes the popular types such as Shadow, Alias, Lock, Trigger-Buffer and Counter (only to name a few). Creating the RTL for these special registers may be easy to do for some experts but modeling them in UVM and manually creating the test environment with 100% functional coverage can be daunting.
Register Verification ChallengesAlthough full-blown in-house scripts are available in large international SoC companies capable of generating RTL, UVM register model and a working UVM verification environment, most lack in several key areas for verification and do not provide 100% functional coverage. On average the standard UVM sequences provided as part of the UVM give less than 50% functional coverage out of the box. The in-house scripts still need to address the following verification challenges:
How to Automate a Complete Register Verification EnvironmentThe good news is that all this can be automated to a great extent so that verification teams do not have to spend the time manually developing the required verification environment, tests and test plan. The automatic register verification solution should employ the components and setup depicted in Figure 1. Figure 1: Components of Automatic Register Verification Mainly, you should be able to dynamically take in Address Map specification in the form of Word/Excel/FrameMaker or textual standards like SystemRDL, IP-XACT or RALF. From the specification, you can auto-generate the following for a simulation-based environment:
If you’d like to see working examples of this automation and the generated results, feel free to contact us. I invite you to view our on demand webinar, 5 Special Registers Useful for Today’s SoCs – Use Cases, Examples and UVM Verification Best Practices. We introduce to you 5 special registers that are widely adopted in the industry. We provide their benefits, use cases and examples (RTL, UVM model and C-Header Files). We also provide best-practices on how to verify them where you can achieve 100% functional coverage. In addition, we touch upon a subject that’s very important for large SoC developers, and that is performance of the register layer. Tags: Embedded, Emulation, FPGA, Functional Verification, ISequenceSpec, Prototyping, SemiEDA, UVM, Verification Category: Registers This entry was posted on Tuesday, December 4th, 2018 at 9:06 am. You can follow any responses to this entry through the RSS 2.0 feed. You can leave a response, or trackback from your own site. |