Agnisys Automation Review Louie De Luna
Louie is the Director of Marketing and Sales at Agnisys, Inc. He has over 15 years of experience in FPGAs, ASICs and EDA industries. Louie was most recently the Director of Marketing for Aldec where he was instrumental in the development and execution of the strategy for the entire functional verification solutions. He received his B.S. in Computer Engineering from University of Las Vegas, NV in 2001. « Less Louie De Luna
Louie is the Director of Marketing and Sales at Agnisys, Inc. He has over 15 years of experience in FPGAs, ASICs and EDA industries. Louie was most recently the Director of Marketing for Aldec where he was instrumental in the development and execution of the strategy for the entire functional … More » What ARE the Root Causes of Functional Flaws?November 1st, 2018 by Louie De Luna
Functional flaws in our everyday electronics are annoying. Internet routers can suddenly stop working, or our smart phones can suddenly freeze. For safety-critical systems such as the airplane engine control system, functional flaws can be catastrophic, and can lead to fatalities of all passengers. For both consumer-type and safety-critical systems, ASIC/FPGA teams strive to minimize functional flaws to the best of their abilities using their verification prowess with the help of EDA tools. The more the budget the better the resource they have for minimizing functional flaws. I just attended the webinar about the results of the Wilson Research Group & Mentor’s 2018 Functional Verification Study, and I can say that I’m not surprised with the results regarding root causes of functional flaws – this is what my team and I come across with frequently when we talk to our prospective customers and verification community.
Confirmed by the 2018 study, the three major causes in ASICs are categorized by Design Error, Changes in Specification and Incorrect/Incomplete Specification. When you combine the two categories related to specification, you can see that the functional flaws caused by issues related to specification is higher than issues related to design error. For FPGAs, the results are the same – the specification is the main culprit. For the rest of this article, we invite you to visit the Agnisys Blog.Tags: ASIC, DO-254, Embedded, FPGA, functional safety, Functional Verification, hsi, IDesignSpec, Specification, Verification This entry was posted on Thursday, November 1st, 2018 at 8:56 am. You can follow any responses to this entry through the RSS 2.0 feed. You can leave a response, or trackback from your own site. |