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 Agnisys Automation Review

Archive for December, 2018

Automating Register Verification with 100% Functional Coverage

Tuesday, December 4th, 2018

UVM has certainly improved reusability of verification environments for SoC projects, significantly lowering the verification costs throughout the electronics industry. Since Accellera’s release in 2011, UVM is now an IEEE standard published as IEEE 1800.2-2017 – IEEE Standard for Universal Verification Methodology Language Reference Manual.UVM has definitely gone a long way.

The UVM Register Layer classes have been quite useful for modeling memory-mapped registers and external memories in a DUT in which users are able to abstract the verification environment and standard tests from block to system level seamlessly with only minimum modifications. However, today’s average electronics consumer demand new use cases at ever-increasing speed and bandwidth – which certainly challenges SoC architects, designers and verification engineers, requiring them to be more creative in the implementation and modeling of the hardware/software interface (HSI). Modeling special registers is needed in order to meet special register behavior, which includes the popular types such as Shadow, Alias, Lock, Trigger-Buffer and Counter (only to name a few). Creating the RTL for these special registers may be easy to do for some experts but modeling them in UVM and manually creating the test environment with 100% functional coverage can be daunting.


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