Warning: Undefined array key "upload_with_nude_flag" in /www/www_com/htdocs/get_weekly_feature_ad.inc.php on line 69
Introduction
In many industries there is a proverbial wall between those who design (designers, engineers, draftspersons, …) and those who manufacture, build, construct or process a product. The image is that the design is thrown over the wall with little attention given to the needs of those on the other side. It would seem axiomatic that tearing down this wall or at least poking holes in it should be beneficial.
Several decades ago I worked for an Architectural/Engineering firm that designed major projects such as fossil fuel power plants and hydroelectric plants. A chronic problem in the industry was the discovery in the field of interferences between beams, HVAC ducts, pipes, electrical raceways, lighting fixtures, pieces of equipment and so on that appeared on the drawing to occupy the same physical space. Since this was physically impossible, something had to be moved in the field. Regardless of what was moved, some engineering design drawings were now wrong. Any engineering analysis related to the item(s) moved was now suspect. The updating of drawings to As Built and the rerunning of analysis programs was a typically a haphazard affair. Further, there was a cost in time and dollars incurred by the contractor to relocate the offending item(s). It was not uncommon to have thousands of interferences of varying degrees of seriousness in a major construction project. The two most common techniques to identify possible interferences during the design phase were isometric drawings of combined engineering disciplines in regions of likely interferences and the construction of scaled models. The two approaches were error prone and had difficulty keeping pace with the design teams. I was part of a small software group that developed a computerized system to collect data from paper drawings, construct a model of the plant and report on the interferences. The system was used on several projects with considerable success. Today commercial plant design programs offer similar capabilities. They also enable a designer in one engineering discipline to work in the context of the other disciplines even referencing items in those disciplines.
Over the years that has been considerable press in the mechanical CAD industry on design for the “ilities”: quality, assemblability, manufacturability, testability, maintainability and so on. Much of the touted benefits of Product Lifecycle Management (PLM) and its predecessor Simultaneous or Concurrent Engineering are attributable to the sharing of design information during the early stages of a product lifecycle with those responsible for downstream tasks. Collaboration is the key. Within the MCAD arena there are numerous applications (stress, fluid, hydraulic, thermal, kinematics, dynamics … ) to evaluate the performance of a design. There are also many Computer-Aided Manufacturing solutions for driving numerically controlled machines (drill, mill, lathe, punch, laser, and edm), coordinate measuring machines and robots. And there are programs for simulating the manufacturing flow. The same software used to design parts can be used by manufacturing engineers to design tools, jigs and fixtures. Having libraries or catalogs of standard parts, helps reduces part count, lowers procurement time and costs and reduces manufacturing risk and cost. Interference and clearance calculations along with animation capabilities can be used to assess assemblability. Design rule check can be driven by user defined features. For example, user defined holes can be used to restrict holes to allowable sizes and shapes. However, DRC is far less pervasive than in the semiconductor world. There are few mechanical applications that can be truly be classified as Design for Manufacturing.
Compared to the architectural and mechanical industries, the semiconductor industry has considerably more time pressure, shorter product lifetimes and more rapidly changing technologies. As the industry moves from process node to process node, the physical limits of manufacturing technology are being challenged. This situation has increased the need for Design for Manufacturing as reflected in the comments of executives from leading EDA vendors.
At the DAC in June Wally Rhines, President and CEO of Mentor Graphics, gave a keynote address entitled: “EDA Industry Growth - Are there enough new problems to solve? (that people will pay for?)”. He answered his own question in the affirmative. He further identified new EDA methodologies as the primary source for growth as it has been in the past. From a short list of possible candidates to drive the next wave of growth he nominated Design for Manufacture. He was confident in his nomination because it is already growing at such a pace (from $200M to $500 million in less than 5 years) that it is preordained. It has the largest growth rate in the industry. Resolution Enhancement Technology (RET), the first wave of DFM, has grown in a few short years from essentially $0 to a couple hundred million dollars. The reasons for DFM's growth are:
|
- Enormous potential cost savings for semiconductor manufacturers
- Extended lifetimes of existing photolithography equipment - Yield enhancements at sub-100nm feature size - EDA expenditures are a nit compared to capital goods equipment budgets and manufacturing cost of goods sold |
On Feb. 24, 2004 Magma Design Automation Inc. announced the signing of a definitive agreement for the acquisition by merger of Mojave, Inc., a developer of advanced technology for integrated circuit manufacturability and verification. Rajeev Madhavan, Magma's chairman and chief executive officer, said "Design for manufacturing, or DFM, issues will continue to gain importance as designs shrink toward 65-nanometer and smaller geometries." and “We believe that performing DFM analysis and correction concurrently with implementation leads to a better quality design, which in turn leads to improved manufacturability.”
On June 7, 2004 Cadence Design Systems, Inc. and ASML MaskTools, announced a software licensing and joint development agreement for advanced resolution enhancement technology (RET) software solutions. The two companies will work together to develop a tightly integrated design for manufacturability (DFM) flow. Lavi Lev, Cadence EVP and GM said "The extension of optical lithography techniques at and beyond 65 nm emphasizes a new level of interdependence between design and lithography. Our customers want to shorten production ramp and improve volume production yield through the use of the most advanced design tools linked to the most advanced technologies for resolution enhancement."
Lithography
Before investigating the current sate of DFM, let us first review the fabrication process for ICs. To make an integrated circuit a layer of either electrically insulating or electrically conductive material (i.e. metal, polysilicon, oxide) is deposited on the surface of a silicon wafer. This material is then coated with a photosensitive resist. An image of a photomask containing a precise image of the circuitry is projected onto the wafer. The wafer is developed and then etched to remove material from the areas exposed with the photomask image.
A new layer of material and resist is then deposited on the wafer and the image on the next photomask is projected onto it. Again the wafer is developed and etched. This process is repeated until the circuit is complete. If the image on the photomask is projected several times side by side onto the wafer, this is referred to as stepping and the photomask is called a reticle.
A photomask consists of a quartz or glass plate covered with a very thin layer of chrome which, in turn, is covered with an AR (anti-reflecting) coating and a thin layer of photoresist. A beam of electrons or a laser beam energizes the photoresist in those areas where a circuit feature is to be created. This exposure causes a change in the solubility of the photoresist, enabling these selected areas to be dissolved. The mask is now etched, i.e. an acid is applied, which dissolves the unprotected chrome, leaving the circuit pattern in the remaining chrome. Finally, the mask is cleaned and covered with a protective pellicle to prevent any subsequent contamination. The photomask is used as a “master” by chipmakers to optically transfer these images onto semiconductor wafers.
The lithography equipment can be electron beam or laser. Laser pattern generators are raster-scan tools that scan the entire mask. Consequently, their write-times are more or less pattern-independent. Vector or variable shaped beam pattern generators scan and write only where patterns are to be exposed, which can result in longer write times as the writer moves from area to area. Because they have faster write-times, lasers are significantly less costly to use than e-beams. However, VSB pattern generators have greater pattern fidelity.
Lithography tools have already been pushed to the point where the minimum feature size of the circuits is smaller than the wavelength of light that can be projected through the mask to create them (see figure). In other words, feature-size scaling has advanced faster than the rate of wavelength scaling.
|
The minimum feature size that may be printed with an optical lithography system is determined by the Rayleigh's equation:
where k1 is the resolution factor, λ is the wavelength of the exposing radiation and NA is the numerical aperture. k1 is a complex factor of several variables in the photolithography process. The trend has been for k1 to fall. The practical lower limit for k1 is thought to be greater than 0.25. Today Argon Fluoride (ArF) Excimer lasers are used with λ = 193nm. Beyond ArF there are Fluorine Excimer lasers (F2) with λ = 157nm, but there are still a number of technical challenges to overcome. Improvements in lens design have led to improvements in the NA of exposure systems lens. Today exposure systems are available with an NA greater than 0.8. The physical limit to NA for exposure systems using air as a medium between the lens and the wafer is 1 and the practical limit is about 0.93. See the Appendix for future developments in lithography.
As the industry moves from process node to process node the trends have been ones of lower initial yield in manufacturing, slower yield ramps and lower mature yields. According to PDF Solutions “As a result of increasing complexity, the introduction of new manufacturing materials, and shorter time-to-volume demands, there has been a shift in the root causes of yield loss toward integration issues from contamination. Yield integration issues are primarily systematic in nature, due to incompatibility between design and process, and failure to meet required specifications”
Several problems arise from the small size of features and the finite size and inherent limitations of the imaging system. First, the high frequency components required to reproduce the sharp edges in polygon features may fall outside the lens. Secondly, stray light entering the opening from one shape may find its way into another shape in close proximity, leading to a complex interaction of the electric fields of adjacent polygons. Thus the final shapes will have rounded corners and may bulge towards adjacent shapes, possibly shorting together and rendering the chip defective if the situation is bad enough.
Resolution enhancement techniques (RETs) have been developed to reliably create smaller features at a given wavelength or to reduce intra-die and inter-die parameter variations, thereby improving yields. The most common RETs are optical proximity correction (OPC) and phase-shift masks (PSMs),
Optical Proximity Correction is the process of modifying the polygons that are drawn by the designers to compensate for the non-ideal properties of the lithography process. Gone is the era of WYSIWYG. Given the shapes desired on the wafer, the mask is modified to improve the reproduction of the critical geometry. This is done by dividing polygon edges into small segments and moving the segments around, and by adding additional small polygons (serifs and hammerheads) to strategic locations in the layout that stretch out the ends of lines and sharpen the corners. The addition of OPC features to the mask layout allows for tighter design rules and significantly improves process reliability and yield
OPC software is divided into rule-based relying on a pre-defined rule set and model-based where corrections are made according to lithography simulations. In the former case special test chips are exposed to characterize the behavior of linewidth as a function of feature size, spacing, orientation, local pattern density, position in the exposure field, and other systematic layout parameters. Software tools identify those that are suitable for OPC. Error functions are inverted to correction functions in the form of design rules. In the latter case the simulated image of the modified layout using optical and process models is compared to the target pattern to determine the need for further layout manipulation. Iterations continue until the optimum match between simulated image and target pattern is found within the constraints of mask manufacturability. Rule-based OPC is simpler to implement but may not cover all situations. The challenge is to create a complete rule set. Model-based OPC results in very long computer runs and large data sets (50-100GB) requiring distributed parallel processing. The definition of OPC has changed to Optical and Process Correction to reflect the inclusion of non-optically related issues.
Attenuated Phase Shift Masks (AttPSM) or Embedded PSMs use materials such as molybdenum silicide rather than chrome. Unlike chrome, this material allows a small percentage (<10%) of the light to pass through. The thickness of the material is chosen so that the light that does pass through is 180° out of phase with the light from the neighboring clear quartz areas. The light that passes through these areas is too weak to expose the resist, however destructive interference occurs any time there is a change from the coating material to the glass. The result is a sharper intensity profile which allows smaller features to be printed on the wafer.
Alternating Aperture Phase Shift Masks (altPSM) utilize selectively etched quartz areas. This etched area causes the light to become 180° out of phase with the light passing through the unetched regions. This would cause any overlapping light from two adjacent apertures to interfere destructively, thus reducing any exposure in the center 'dark' region. This type of PSM is most effective on device patterns which are highly repetitive and closely spaced.
Other OPC techniques include Off-Axis Illumination (OAI) such as quadruple and annular illumination, scattering bars (SB) and sub-resolution assist features (SRAF). In addition to optical and process effects that impact yield there are also antenna effects (charge accumulation of interconnect components), planarity (the difference in oxide heights for given region on a design due to chemical mechanical polishing) and via reliability issues.
The historic approach to DFM is similar to the advice that the physician gave to his patient that complained that it hurts when I do this. The doctor response was “don't do that”. The output of fabrication is analyzed and characterized. Factors that negatively impact yield and performance are examined to uncover the root causes. A set of manufacturing design rules or practices to avoid or minimize these contributing factors is codified so that designs can be checked against them. These rule sets are unique to the equipment and processes of a specific foundry. In the past design rules checks had a clear yes/no or pass/fail definition on what could be manufactured. Today, rules relating to yield are more probabilistic to reflect process variations. There are also interactions on issues of functionality, performance, power and yield. There is a need for both feedforward and feedback mechanisms between design and manufacturing.
According to John Ferguson of Mentor Graphics “... a new paradigm is required in verifying IC layouts. Rather than simply providing information on a pass/fail basis, designers need immediate access to how various layout characteristics impact the chip yield. Such an approach would enable the identification of trouble spots and allow implementation of layout improvements, as well as some quantification of how much yield improvement the change to the layout allows. A complete data/layer analysis/feedback methodology gives designers and CAD managers the ability to make decisions and take control over which issues will be corrected and at what level of correction. This results in a yield greater than that created by simply meeting the design rules and guidelines.”
Joseph D. Sawicki, VP & GM of Mentor Graphics' Design-to-Silicon Division adds: “How do I define DFM? For one thing, it's not a noun--it's an adjective that means to extend and expand current design flows to optimize for manufacturing. DFM supposes that design matters and how functionality is put onto silicon positively or negatively effect the manufacturability of the design. DFM represents tools and processes that intelligently leverage extensive design rule expertise, account for the impact of parasitics on timing and power, and work to detect and pinpoint areas of concern, whether they be performance degradation or yield loss. It is a deepening of the connection between physical verification, post-layout applications (such as OPC-optical and process correction), and design for test. DFM will give the designer the ability to conduct a cost/yield analysis on full chip data, optimally trading off size, performance and yield.”
The diagram below from MEDEA (Micro-Electronics Development for European Applications) shows the desired foreword and feedback paths for information exchange. Given the situation plus the exploding size of GDSII file it is not surprising that there are already efforts underway to define a more compressed and comprehensive data format.
|
Diagram showing information flow for DFM
Source: MEDEA Micro-Electronics Development for European Applications |
Semiconductor Equipment and Materials International (SEMI) rolled out the Open Artwork System Interchange Standard (OASIS) in September 2002 as a replacement for the GDSII file format, and said it promises a tenfold reduction in design data compared to GDSII while improving the quality of information. OASIS is a specification for hierarchical integrated circuit mask layout data format for interchange between EDA software, IC mask writing tools and mask inspection tools. OASIS is an open, broadly applicable, interchange method and set of interrelated ideas and principles that define illustrative design data elements as geometric data. OASIS was approved by the SEMI worldwide lithography committee in July 2003. In addition to file size reduction OASIS efficiently handles flat geometric data, including arrayed geometric figures; removes 16-bit and 32-bit restrictions, allowing integers to extend to 64 bits and beyond when required; and enhances overall information richness.
In June 2004 Mentor Graphics announced a free GDSII-to-OASIS translation utility available for download from its website.
Silicon Integration Initiative (Si2) is an organization of industry-leading silicon systems and tool companies focused on improving productivity and reducing cost in creating and producing integrated silicon systems. In June 2004 Si2 announced the formation of the Design to Mask Coalition (DTMC). The idea had surfaced at a design for manufacturing "summit meeting" hosted by SEMI in August 2003. The goal of DTMC is to speed photomask and wafer manufacturing ramps and improve yields through the communication of more detailed and comprehensive design, mask, and wafer process information, resulting in lower manufacturing costs and shorter cycle times for the manufacturing of integrated circuits.
What has been proposed is the development of a Unified Data Model (UDM), a common design-through-manufacturing data model. The Semiconductor Equipment and Materials International (SEMI) Universal Data Model working group had already endorsed the OpenAccess data model and API as the basis for a more intrinsic, comprehensive design chain data link between IC design and manufacturing. OpenAcess has been the main Si2 project providing an open standard and data API and reference database supporting that API for IC design. The DTMC will lead the OA-UDM industry project under Si2 to deliver the UDM with supporting technology.
Appendix on Lithography Future
According to the INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS (ITRS) 2003 EDITION on LITHOGRAPHY:
|
“Optical lithography is expected to be the dominant approach through the 65 nm node, with Next Generation Lithography (NGL) possibly appearing at the 45 nm node, although more likely later. … Perhaps the most significant decision to be made regarding potential solutions involves immersion lithography. If this technology proves viable, it has the potential to extend 193 nm imaging to the 45 nm node, thus delaying or obviating the introduction of 157 nm lithography. Immersion lithography could extend optical lithography close to the 32 nm node if it can be implemented using 157 nm light. Thus, immersion lithography has an impact on the possible implementation of 157 nm lithography,
and then later on the timing for the insertion of next-generation lithographies.
The post-optical or next-generation lithography alternatives are all candidates at and below 45 nm. Of the possible NGL technologies, multiple regions consider EUV, EPL, maskless (ML2), and imprint lithography as potential successors to optical lithography. ... Although many technology approaches exist, the industry is limited in its ability to fund the simultaneous development of the full infrastructure (exposure tool, resist, mask, and metrology) for multiple technologies. ... The introduction of non-optical lithography will be a major paradigm shift that will be necessary to meet the technical requirements and complexities that are necessary for continued adherence to Moore's Law at the 32 nm node and beyond. This shift will drive major changes throughout the lithography infrastructure and will require significant resources for commercialization. These development costs must necessarily be recovered in the costs of exposure tools, masks, and materials.” |
Weekly Highlights
Intel Updates Third-Quarter Business Expectations; Revenue Expected to be Between $8.3 Billion and $8.6 Billion
MVC Capital Announces Sale of 0-In Design to Mentor Graphics for Stock; Fund to Record an Additional NAV Increase of $.05 Per Share
Cadence Approved to List on NASDAQ and NYSE Exchanges
HDL Works BV Presents EASE™ 5.2
Silicon Canvas Releases Laker-AMS Version 6.1 with Schematic-Driven Full Custom Layout Flow
IPCore Technologies Adopts Synopsys Solution as Primary Design Flow
Shanghai Research Center for Integrated Circuit Design and Cadence Introduce New CPU/DSP Core-Based Methodology for SoC Chips
Synopsys Introduces Industry's First 90 Nanometer USB 2.0 On-The-Go PHY and Extends Its Hi-Speed USB PHY to 90 Nanometer Node
Samsung Standardizes on Synopsys DesignWare USB IP
Cadence Accelerates Time to Market for Stretch; Comprehensive Cadence Encounter Digital IC Design Solution Helps Startup Implement High Performance Configurable Processor
Mentor Graphics and Denali Collaborate to Deliver High-Quality Intellectual Property for PCI Express and Advanced Switching Interfaces
HP Outships All Server Vendors Worldwide; Extends Linux and Windows Leadership in Factory Revenue and Units
Synplicity Promotes Gary Meyers to President and COO
AMD Demonstrates World's First x86 Dual-Core Processor; AMD's Newest Leadership Milestone Changes the Dynamics of the Industry
Fairchild Semiconductor Announces Industry's Only Video Filter/Driver to Offer Selectable High Definition, Progressive Scan and Standard Definition Filters
Agere Systems Ships TrueStore(TM) Storage Chips to Magicstor for High-Capacity Mobile Disk Drives
ZSP(R) Cores 'DSP of Choice' for Broadcom's Set-Top Box Audio Applications
RF Micro Devices Announces New Bluetooth System-on-Chip Solution with Enhanced Data Rate; Optimized for Mobile Phone Applications
Alliance Semiconductor Expands Mixed Signal Family to Include the Industry's Most Comprehensive Line of Zero Delay Buffers
More EDA in the News and More IP & SoC News
Upcoming Events...
--Contributing Editors can be reached by clicking here.
You can find the full EDACafe.com event calendar here.
To read more news, click here.
-- Jack Horgan, EDACafe.com Contributing Editor.