Let’s say you have a block you need to verify. How do you know that the stimulus you are about to use is exhaustive enough and that you have covered the necessary scenarios/situations to prove it is working correctly? This is where functional coverage comes in. SystemVerilog’s functional coverage constructs allow you to quantify the completeness of your stimulus by recording the values that have occurred on your signals.
Consider an 8-bit address signal, paddr, and a 32-bit data signal, pwdata. Assigning a coverpoint to each signal will direct your simulator to track these signals during simulation and record the number of hits. For each coverpoint, bins can be created to organize the possible signal values into meaningful categories. Finally, a covergroup is used to encapsulate it all and is instantiated using the new() constructor. Associating the covergroup with a clock event is also a good way to trigger the coverage sampling.
DVCon is a great place to talk to design and verification engineers. As the Accellera Portable Stimulus Standard (PSS) gets closer to reality, we were able to share with them during the conference the progress made and the ways in which it may impact their task. Most of them are as excited about PSS as we are. While we have been working in this field for more than a decade and have received a lot of feedback, there are now many more people becoming aware of it and the potential that it has. This provides us with the opportunity to learn as well.
I like simple things. In particular, I like clean and simple ways to solve a problem. For example, user interaction with an embedded system might be something very slick – touch screen LCDs seem to be fitted to everything nowadays. But sometimes a simple LED indicator is enough. It is amazing how useful a simple blinking light can be …
IC Insights’ latest market, unit, and average selling price forecasts for 33 major IC product segments for 2018 through 2022 is included in the March Update to the 2018 McClean Report (MR18). The Update also includes an analysis of the major semiconductor suppliers’ capital spending plans for this year.The biggest adjustments to the original MR18 IC market forecasts were to the memory market; specifically the DRAM and NAND flash segments. The DRAM and NAND flash memory market growth forecasts for 2018 have been adjusted upward to 37% for DRAM (13% shown in MR18) and 17% for NAND flash (10% shown in MR18).
The big increase in the DRAM market forecast for 2018 is primarily due to a much stronger ASP expected for this year than was originally forecast. IC Insights now forecasts that the DRAM ASP will register a 36% jump in 2018 as compared to 2017, when the DRAM ASP surged by an amazing 81%. Moreover, the NAND flash ASP is forecast to increase 10% this year, after jumping by 45% in 2017. In contrast to strong DRAM and NAND flash ASP increases, 2018 unit volume growth for these product segments is expected to be up only 1% and 6%, respectively.
Skyrocketing DRAM prices potentially open the door for startup Chinese competitors.
In 2017, DRAM bit volume growth was 20%, half the 40% rate of increase registered in 2016. For 2018, each of the three major DRAM producers (e.g., Samsung, SK Hynix, and Micron) have stated that they expect DRAM bit volume growth to once again be about 20%. However, as shown in Figure 1, monthly year-over-year DRAM bit volume growth averaged only 13% over the nine-month period of May 2017 through January 2018.
Figure 1 also plots the monthly price-per-Gb of DRAM from January of 2017 through January of 2018. As shown, the DRAM price-per-Gb has been on a steep rise, with prices being 47% higher in January 2018 as compared to one year earlier in January 2017. There is little doubt that electronic system manufacturers are currently scrambling to adjust and adapt to the skyrocketing cost of memory.
The 2018 CEO Outlook is scheduled for April 5 and you are invited to join us!
This year, we welcome back Arm’s Simon Segars and Wally Rhines from Mentor, a Siemens Business, and thank Dean Drako of IC Manage and Sonics’ Grant Pierce for agreeing to participate in the discussion about the semiconductor design ecosystem. Ed Sperling, editor-in-chief of Semiconductor Engineering, genially accepted our invitation again this year to moderate the panel made up four of our directors.