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 What Would Joe Do?

Posts Tagged ‘Synopsys’

CDNS: What a difference a year [or 2] makes

Thursday, July 26th, 2012

 

We’re coming up on almost four years, full on, since the momentous events of 15 October 2008 when the entire top executive team at Cadence exited stage left.

At the time, of course, the world was paying a shade less attention to EDA, and a shade more attention to a global crisis unfolding minute-by-minute featuring household concepts such as bankruptcy, subprime mortgages, and derivatives, and household names such as Lehman Brothers, AIG, Merrill Lynch, Bank of America, Goldman Sachs, Morgan Stanley, Washington Mutual, JPMorgan, Wachovia, CitiGroup, and the FDIC, to name a few.

Meanwhile, the folks who held CDNS in mid-October 2008 were holding shares that had lost almost 80% of their value over the previous 12 months, plummeting from $20+/share to around $4/share in that time frame.

The world may have been consumed by news of the larger global meltdown in October 2008, but various CDNS shareholders were sufficiently focused on the disaster at Cadence to precipitate upwards of a dozen class-action suits against the company in protest.

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Accellera Systems Initiative: team effort & SystemC Library 2.3

Thursday, July 19th, 2012

 

This week, Accellera Systems Initiative is announcing a new version of its SystemC library, Version 2.3 to be exact. There hasn’t been a new version since way back in 2005 with Version 2.1 (albeit 2.2, a bug-fix release, was published in 2006), so this is the culmination of a lot of hard work.

I spoke by phone with Accellera Systems Initiative Language Working Group Chair David Black, Senior Member of Technical Staff at Doulos, on July 17th.

Black explained, “The purpose of Version 2.3 is to reflect the latest version of IEEE Standard 1666 – to fundamentally demonstrate new features introduced into the SystemC standard, which includes TLM 2.0, previously an OSCI-only standard and now part of the IEEE standard. Interested parties can download the SystemC 2.3 library from the Accellera Systems Initiative website. This download includes several bug fixes, the latest TLM 2.0 and new SystemC features”

I asked Black who has participated in this work, and how often they meet. He said, “The Language Working Group of Accellera Systems Initiative includes all of the major EDA vendors – Cadence, Mentor, Synopsys, and Forte – and service providers such as Doulos and Circuit Sutra – and various members of the industry such as Intel, TI and STMicro, with everyone contributing a perspective.

“I am the Co-Chair of the SystemC Language Working Group along with Andy Goodrich [Forte Design Systems] and took over my position from Mike Meredith [also with Forte]. Key contributors also include Tor Jeremiassen [TI], John Aynsley and Alan Fitch [Doulos], Bishnupriya Bhattacharya [Cadence],  Jerome Cornet [STMicroelectronics],  Dr. Torsten Maehne [UPMC], Pat Sheridan and Bart Vanthournout [Synopsys], and Philipp Hartmann [OFFIS], along with many others.

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MathWorks: the elephant in the room

Wednesday, July 18th, 2012

 

To get to MathWorks’ corporate headquarters outside Boston, take the Red Line to the Orange Line to Back Bay Station. Take the Commuter Rail to Natick, cross the bridge over the tracks, walk north along leafy Walnut Street for a mile and a quarter, turn left onto Route 9, and cross the grass to Apple Hill Drive. Turn left into the parking lot of the company’s campus, pick your way through the construction going on there, and look for the main reception building across from the big parking structure.

If you do all of this, and it’s 90+ degrees with 60% humidity, you’ll be totally drenched by the time you walk into the cool of the MathWorks headquarters. But no worries; the very nice person at the reception desk will send you down the hall to the closest break room where you can get a tall drink from the beverage dispenser and bring it back to the reception area to rest, recuperate, and prepare for your meeting with Ken Karnofsky.

Okay, two points of interest here: a) MathWorks is different. It’s headquartered in a residential neighborhood, not a commercial park; and b) the welcome is relaxed and not the high-pressure stuff of Silicon Valley.

Two additional points of interest: c) MathWorks is expanding. They’ve got 2400 employees currently, with an additional 200 job openings! Their Natick campus may offer a calm retreat from a humid Massachusetts afternoon, but it’s not a calm retreat from the world because when you’re there, MathWorks feels to be at the center of the world.

And d) MathWorks is definitely an EDA company, even though they don’t belong to EDAC and they don’t exhibit at DAC (although they have exhibited in the past). If you design chips, MathWorks’ MATLAB and Simulink is the gateway into your design. When it comes to EDA, MathWorks is most definitely the elephant in the room.

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Verification update: Breker, EVE & SNPS, CDNS, Agilent & Aldec

Thursday, July 12th, 2012

 

It may be summertime, but the folks in the Verification world are clearly not taking any holidays.

This week, four different verification-related news announcements arrived, presenting an interesting set of positive mid-year perspectives: Breker’s new round of funding, EVE and Synopsys’ co-emulation success, Cadence’s beefed-up PCIe VIP, and a new co-simulation interface from Aldec and Agilent. Good news on all fronts and now these folks should take a vacation!

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SI: What comes after CDNS acquires Sigrity?

Thursday, July 5th, 2012

 

The SI landscape is a confusing one: What is the true value of a signal integrity analysis tool, and if you’re an EDA vendor, do you need to offer an in-house SI solution to be a true end-to-end provider?

Although Cadence has had a position in signal integrity with their OrCAD Signal Explorer [pre- and post-route topology exploration and transmission line analysis, conceptual, pre-design/schematic topology exploration and simulation, routed or unrouted board topology extraction and analysis] …

… this week Cadence announced it has acquired Silicon Valley-based Sigrity and will now incorporate Sigrity’s PowerSI [full-wave electrical analysis for IC packages and PCBs, identifies trace and via coupling, power/ground bounce, and design regions that are under or over voltage targets] and SystemSI [chip-to-chip signal integrity analysis, including parallel bus analysis and serial link analysis, frequency domain, time domain and statistical analysis] into Cadence’s flow.

This all sounds great as a strategy for beefing up Cadence’s SI offerings, but what does it do to Sigrity’s current set of partners: Apache [owned by Ansys], CST, Mentor Graphics, Synopsys’ HSPICE, TSMC, and Zuken?

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49DAC Unplugged: Bob, Chris, Ry, Steve, Jennifer, Wally, Jill, Lee

Monday, June 4th, 2012

 

DAC started with a boom on Sunday night, June 3rd. EDAC reports that 900 people registered for the opening reception, and by the crush of people in Salon 7 in the basement of the San Francisco Marriott Hotel, it looked like everybody showed up. [Although perhaps not quite 900…]

Setting up my word processor on a cocktail table at the back of the crowd, I manged to see numerous thought leaders in EDA as they swam by, in and out of the stream of people that swirled throughout the wine, buzz & music-laden ballroom as EDAC’s Executive Director Bob Gardner’s Jazz Trio entertained up on stage.

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Joe Costello: Orb, Oasys, Epicenter

Wednesday, May 16th, 2012

 

On May 1st, Joe Costello was standing in his office at Orb Networks on the 6th floor of a building in downtown Oakland. When we started our phone call, he said, “I’m looking down on Broadway and there’s a massive march out there. It’s crazy — wish I could send you the video!”

It was, of course, the May Day Occupy Oakland march, which seemed just about right for this long-planned interview.

Twenty years ago, Joe Costello was CEO at Cadence; today he’s President & CEO at Orb Networks, a company that’s “cranking away at cool stuff in the media space.” Twenty years ago, Joe Costello was the epicenter of EDA; today he’s roiling things up elsewhere in the technology ecosystem.

So first we talked about Joe’s present and future, and then we got around to EDA’s present and future and What Would Joe Do if he was back in the epicenter today.

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DAC 2012: Terrible Tuesday in San Francisco

Tuesday, May 8th, 2012

 

DAC looms!

And never more so than on Tuesday — especially this year, June 5th, when you’re going to have to make some terrible decisions about what to miss, and what not to miss.

First there’s the opening session in the morning when a boatload of awards are handed out, followed by the 2012 keynote. The Exhibition Hall won’t open until these things wrap up, so other than company meetings or company special-product announcement breakfasts, you should be able to be in the main theater at Moscone from 8:30 to 10:00 am or so.

Of course, worst case scenario: The opening session at DAC is always video-taped, so you could watch it at a later date after it’s uploaded to the DAC website but that’s hardly ideal.

This year’s main address will be delivered by ARM’s Mike Muller, “comparing the original ARM design of 1985 to those of today’s latest microprocessors … how far design has come and what EDA has contributed to enabling … systems, hardware, operating systems, and applications.” Then Muller plans to talk about 2020, how to get there, and what it will be like when we do. Conclusion? This stuff’s better heard in person than tape delayed. Go to the opening session, and plan not to regret it.

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SAME: Microelectronics in the South of France

Thursday, May 3rd, 2012

 

The Sophia Antipolis Microelectronics Forum takes place every fall in the ‘Silicon Valley’ of Southern France, Sophia Antipolis, 5 miles inland from the beautiful Mediterranean city of Antibes.

Sophia Antipolis is about 20 minutes from the International Airport at Nice, with offices for approximately 800 high-tech companies – included among them: ARM, Broadcom, Cadence, HP, IBM, Infineon, Intel, Mentor Graphics, Nvidia, STMicro, and Synopsys – housed in a range of buildings set among the rolling hills of the enclave. Within that forested place and 800 enterprises, almost 40,000 people are employeed. There are also two college campuses in Sophia Antipolis, as well as restaurants, a golf course, multiple hotels, and a tennis institute.

In other words, if you’ve never been to the Cote d’Azur, never been to Nice or Antibes, if you think you’d love vistas across the wide blue Mediterranean Sea, want to learn more about good food, wine, Picasso, Matisse, ancient Greeks, the French Riviera, or microelectronics – and not necessarily in that order – you’re going to be wanting to go to the Sophia Antipolis Microelectronics Forum taking place this year on October 2nd & 3rd.

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Rajeev Madhavan: The Road Not Taken

Tuesday, April 24th, 2012

 

There’s good news and bad news, in my opinion, with regards to Rajeev Madhavan, founder and CEO of Magma Design Automation, a company that was acquired by Synopsys on February 22, 2012.

The good news it that Rajeev is available to the press for candid interviews like the one included below. The bad news is Rajeev is not going to be part of the EDA landscape as he explores various options for the next phase of his life – and that means the industry will be just that much less interesting, at least for a while.

We spoke by phone in late February.

***********************

Peggy: Hey, Rajeev, how are you doing?

Rajeev: I’m doing pretty much okay as I think about what’s next. I’ve got opportunities, and I’ve got other interests I can now pursue – most people rarely get this kind of opportunity in life, so I’m grateful.

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DownStream: Solutions for Post Processing PCB Designs
TrueCircuits: UltraPLL



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