What Would Joe Do?
Peggy Aycinena is a freelance journalist and Editor of EDA Confidential at www.aycinena.com. She can be reached at peggy at aycinena dot com.
January 10th, 2013 by Peggy Aycinena
EDA veteran Dr. Walden Rhines, Mentor Graphics CEO & Board Chairman, is one of the keenest and most optimistic observers of the industry. We spoke this week about the recent EDAC Market Statistics Service [MSS] numbers for Q3 2012.
Per Rhines: “EDA is growing at a rate almost a percentage greater than a year ago and most strongly in the Asia Pacific region, while also growing in other regions as well. [Only] Japan is not growing.”
He said there is growth in all product areas, but the “biggest growth is in the areas of new methodologies. ESL is very strong, and interestingly on the PCB side [growth was seen in] analysis tools such as signal integrity. But packaging is also growing, strongly consistent [with growth] in the new methodologies.”
Rhines also noted that CAE strength was largely influenced by growth in hardware-assisted verification (a.k.a. emulation), as well as the already mentioned ESL design.
“There’s actually healthy growth in everything,” he said, “except design verification and physical design and verification, which are both a little bit down. That’s largely caused by place-and-route, although detailed layout continues to be strong. [To be specific], the big category in physical design and verification is fine, and yield enhancement is fine, but standard place-and-route is weaker. If I had to come up with a reason, everything tends to have its ups and downs, so [in the long run] even place-and-route is still a good growth area.”
January 3rd, 2013 by Peggy Aycinena
As the New Year dawns, it is time to think about DAC 2013 happening from June 2nd to 6th in Austin, Texas. Of the many appealing aspects to the Design Automation Conference, the Designer/User Track that has been brought online over the last several years is one of the best. Hence it is important to note the deadline for submissions for the D/U Track is a brief month away — February 6th.
January 3rd, 2013 by Peggy Aycinena
Last night, Judy Collins gave a holiday concert at Davies Hall in San Francisco to a sold-out crowd of acolytes. Only an artist of Collins’ fame would be allowed to ofttimes warble off-key, forget the occasional lyric, and natter on in and around the music, yet still receive a standing ovation. After all, at 73 she is still full of performing fire, still full of attitude and life. Her appearance at Davies was a celebration of that life, lived to the fullest and in many different spheres.
Last week, U.C. Berkeley’s EECS Department threw a birthday party/symposium for Chenming Hu in Sutardja Dai Hall for an SRO crowd of past students, present students and acolytes, friends and family. Only an educator and technologist of Hu’s stature – former CTO of TSMC, ‘father’ of the FinFET, ‘godfather’ of BSIM and an international expert on CMOS device models – would be honored thusly in his 65th year by the University, and allowed to hand pick the list of speakers who filled the day-long event.
Not the least among those chosen was Ramune Nagisetty, a former MSEE student of Hu’s, who now leads a team at Intel/Hillsboro. Nagisetty recently added self-taught guitarist and vocalist/lyricist to her CV, and no matter that she ofttimes warbled off-key during her lunchtime and mid-afternoon performances during the symposium, and nattered on in and around her music, she still received a jumped-to-their-feet ovation from Hu et al.
That’s because Nagisetty was just one part of the evidence offered on December 13th – talks, demonstrations, and performances – to prove that Chenming Hu’s life to date has been lived to the fullest and in many different spheres: His family was in attendance to celebrate with the crowd, Hu’s paintings, and those of his wife and sons, were on display in the lobby outside Banatao Auditorium, Nagisetty’s music was presented, and a remarkable group of technologists as diverse as …
December 13th, 2012 by Peggy Aycinena
When it comes to stimulating, it doesn’t get better than stepping out of a session at IEDM in San Francisco to take a conference call from Glasgow. On Tuesday, December 11th, I stepped out of Session 9 and a presentation on spintronics to speak with Dr. Asen Asenov about a different device technology.
Asenov is a 20-year veteran of the University of Glasgow, where he serves as James Watt Professor of Electrical Engineering and heads up the Glasgow Device Modeling Group. He is also founder of Glasgow-based Gold Standard Simulations (GSS), a company that specializes in simulating statistical variability in nano-CMOS devices.
We spoke on December 11th because GSS announced that day the results of research “comparing the differentiation between metal gate first and metal gate last FDSOI [fully-depleted silicon-on-insulation] approaches, and comparing it to equivalent bulk MOSFETs.” Based on that work, the company announced that gate-last technology “offers significant advantages” over gate-first technology for devices built on 32- or 28-nanometer FDSOI, and noted that both nodes “significantly outpace equivalent bulk MOSFETS with respect to low-power SRAM design.”
December 6th, 2012 by Peggy Aycinena
Shakeel Jeeawoody is VP of marketing at Blue Pearl. I enjoyed a long conversation with Shakeel at SAME Forum in France in October, and again at ARM TechCon in November. We completed the discussion by phone this week, starting with a brief profile of Blue Pearl and a discussion of FPGA versus ASIC design needs.
Per Jeeawoody, “Blue Pearl has been around since 2005, we’re located in Santa Clara, and our technology has all been developed in-house. Our underlying technology improves RTL analysis using symbolic simulation techniques and adapting them to our customers’ market requirements. We have competitors in the linting and clock-domain crossing [CDC] space, but not many that can generate SDC constraints and offer easy-to-use tools that run on Windows at an attractive price point to support FPGA designers.
“More FPGA designers today struggle with IP integration in their projects in the same way ASIC designers have in the past; if they don’t do the right level of analysis, there are reliability problems in the field. With that in mind, we focus on addressing emerging and major FPGA design issues – one we call Grey Cell Methodology, and we offer mode-based analysis to address issues associated with longest path analysis.
November 29th, 2012 by Peggy Aycinena
You’ve got a little over a week to clear your calendar to attend two very important conferences spanning the week of December 10th to the 14th. IEDM is happening in San Francisco from December 10th to 12th, and the 3-D Architectures for Semiconductor Integration and Packaging Conference is happening in Redwood City from December 12th to 14th.
These are two well-attended and carefully constructed conferences which many people attend to learn about the latest in device engineering and 3D-IC architectures, both key to the future of the semiconductor industry.
Clearly, December is a busy month. If you’re in Sales, you may be trying to maximize your numbers for the quarter, and the year, over the remaining weeks of 2012. If you’re in R&D, you may be trying to utilize budget dollars that come with ‘use it or lose it’ strings attached. If you’re in Field Support, your customers are stressed, short on time, and need your attention sooner, not later, so they can wrap up their projects before their holiday leave begins. And if you’re that customer, the Designer trying to meet a development schedule, you are really strapped for time.
November 22nd, 2012 by Peggy Aycinena
If you are looking for an opportunity to express your satisfaction with a colleague’s contributions to the world you work in, two outstanding chances currently present themselves. But take care: The deadlines for submitting your nominations quickly approach.
First, Accellera Systems Initiative [a.k.a. Accellera] has set January 18th as the deadline for submitting nominations for its 2013 Technical Excellence Award. Per the organization: “The Award recognizes outstanding contributions in the creation of EDA and IP standards [which are then contributed to the IEEE Standards Association] by a member of an Accellera technical committee.
“Any individual who is a member of an Accellera technical committee is eligible to receive the award, which will be presented at Accellera Systems Initiative Day during DVCon 2013 next February in San Jose. Candidates may be nominated by the industry at large and are endorsed by Accellera committee members. To nominate an individual, visit Accellera.org.”
If you want to do something really dramatic, however, the EDA Consortium is currently accepting nominations for its annual EDAC/CEDA-sponsored Phil Kaufman Award, which these organizations frequently refer to as the Noble Prize of EDA.
November 14th, 2012 by Peggy Aycinena
It’s a bit early for New Year’s Resolutions, but Real Intent has gotten a jump on the popular annual ritual. As of today, the company is declaring “a bold new look for its corporate logo and Web-site, and a new location for its headquarters.”
The press release reiterates Real Intent’s offerings – Ascent, Ascent Lint, Ascent Implied Intent Verification, Ascent X-Verification System, Meridian, Meridian CDC, and Meridian Constraints – and says, “with the capabilities [of these products] in mind, Real Intent re-imagined its logo to mimic the real intent of these software offerings. The familiar white and blue logo now is recast with striking simplicity.
“The new ‘look’ graphically parallels the simplicity and speed with which SoC designers can use Real Intent’s technology. The transformation mirrors Real Intent’s evolutionary change from an EDA formal verification company to a best-in-class verification solution company. Real Intent has also transformed its Web-site with a dramatic, clean new look and simple navigation that parallels the simplicity and ease of use of its solutions.”
Now, you may say that all of this is being done just to catch the eye of a jaded public, but consider how hard change really is.
November 12th, 2012 by Peggy Aycinena
If you’re an IP developer, or somebody who develops SoCs where blocks of IP land, Synopsys is announcing a product today that will be of interest: the HAPS-70 Series. It’s a prototyping system with a distinguished provenance that runs your ASIC-targeted design on FPGAs for validation prior to tape-out.
HAPS-70 started its journey to your work place way back in 1987 when Sweden-based HARDI Electronics was founded. The folks at HARDI developed the original HAPS prototyping system, which became part of Synplicity’s arsenal in 2007 when HARDI was acquired by SYNP, and the product was relaunched as HAPS-54.
Gary Meyers was President and CEO of Synplicity at the time, and was quoted: “This is a major strategic move for Synplicity. We will be able to immediately leverage our existing ASIC verification products (Certify, Synplify Premier, Identify, and Identify Pro) by selling them together with the HARDI ASIC prototyping boards.”
November 8th, 2012 by Peggy Aycinena
It might be the impression of late that all EDA-startup roads lead to Synopsys, but that would be incorrect. Small, privately-held companies continue to make their way in the industry, independent and productive.
Ausdia, based in Silicon Valley, has been underway since 2006 developing tools for timing constraint verification and management. Today the company announced a new board member, Sanjay Lall. Per the press release, Lall has 20+ years of experience in the EDA and semiconductors, “an expert in operations, marketing, fund raising and sales.”
He is also Chairman and Managing Partner at Cronox Group, on the Board of Advisors at Verdigirs Technologies, and a Director at Mobi-holdings. Previously, Lall was VP of Sales at Extreme DA, and “influential in the company’s acquisition by Synopsys in 2011.”
All EDA-startup roads may not lead to Synopsys, but not surprisingly the CVs of most seasoned EDA veterans do lead to Synopsys, and/or to Cadence and/or Mentor Graphics.