What Would Joe Do?
Peggy Aycinena is a freelance journalist and Editor of EDA Confidential at www.aycinena.com. She can be reached at peggy at aycinena dot com.
Homework assignment: Synopsys Discovery VIP
February 28th, 2012 by Peggy Aycinena
Your assignment, should you choose to accept it, is to understand the new VIP product suite out of Synopsys. That’s really not too hard – the press releases, FAQs, and presentations are all out there for the taking, if you just get your act together and do your homework.
Unfortunately, I hadn’t – at least, not before my phone call last Friday, February 24th, with Neill Mullinger, Group Marketing Manager for Verification IP at Synopsys, and Michael Sanie, Director of Verification Product Marketing.
The call went badly, I couldn’t fully grasp the subtleties of their presentation, and I was running late for another meeting. Turns out, if I had just studied the materials beforehand, not only would it have clarified things, we could have skipped the call completely. The info was all there in the marketing collateral.
Here’s what Niell and Michael were trying to tell me.
Synopsys has introduced a new line of Verification IP, implemented in SystemVerilog, which utilizes native UVM, VMM, and OVM methodologies. It’s called Discovery VIP, and it’s been successfully deployed over the last 18 months at various customer sites. However, Synopsys has timed the formal announcement of the product to coordinate with this week’s DVCon 2012, happening at the DoubleTree in San Jose.
In our phone call last week, Neill Mullinger said, “The focus of Discovery VIP is on protocols, and the verification of protocols. In the last few years, protocols have become much more numerous on SoCs, and a lot more complex, as consumers are demanding more features and lower power.
“As a result, we’ve gone from fairly straightforward protocols, to highly interleaved protocols. In turn, that’s created the need for a lot more testing, and for verification engineers on a project to have a lot more to comprehend and debug.
“So, the challenges have increased significantly, along with a jigsaw puzzle of e, Vera, SystemVerilog, UVM, OVM, and multiple layers of base protocols – on top of which are layered whatever the verification engineers need to get it done. There’s baggage in all of those layers, and chaos, which has created limitations on the protocols.”
“Wow,” I said. “Sounds like a mess.“
“It’s not a mess,” Michael Sanie responded, “because people are clearly having success, but the process is not scalable. It’s hitting a wall of management complexity, and is not a long term solution.”
Mullinger added, “In fact, we’ve seen it as an opportunity to create a next-generation of VIP, to create something that’s more aligned with where the industry is headed. We’ve worked to develop something that verification engineers can use to test quickly, debug effectively, and get into coverage closure more confidentiality, which means being able to test the progress of their verification against their test plan.”
“So,” I asked, “do I have to throw out everything I’ve been using? Do I have to start from scratch learning how to use this new stuff?”
Mullinger was polite, “No. Anything you’ve been using for the last 10 years won’t change, but going forward you’re going to have to use a new approach for VIP. And, as our customers are migrating to UVM, Discovery VIP will be the natural direction for them to adopt, because it’s very, very helpful to the verification engineers.”
Sanie was also polite, “We’re not suggesting customers throw out anything, regardless of what simulator they’re using. However, as they move to UVM, this will be the product that gives them a big, big step forward in productivity, as well as the tools they need that go with it.”
“And what do those tools include?” I asked.
Sanie answered, “ A configuration creator, a test plan, a protocol analyzer, built-in coverage, a library and test suites.”
“And how much is it all going to cost?” I asked, clearly anxious to get on with things.
Sanie remained cool, “That’s actually too complex to answer. It depends on the size of the testbench.”
“And what about the stuff I already own?” I asked.
Mullinger was reassuring, “We’re continuing to support DesignWare VIP. This is just a new line targeted at much better productivity for UVM or SystemVerilog.”
“So it’s not a replacement, and it’s not for everybody.” I concluded.
Mullinger countered, “VIP is different from tools. It’s a building block. If you start a new project, you would use this on your next generation product. It’s like building a new hose. You wouldn’t use old windows on a new house.”
“And how hard will it be to learn?” I asked.
“Not hard,” Sanie answered.
“Okay – so in 25 words or less, what exactly are you announcing?” I demanded.
Mullinger offered, “The solution [to verification] is to start with a new VIP architecture, an architecture that’s open, and scalable to the evolving complexity – and that’s what we’re announcing.
“Discovery VIP is a new family of VIP based on a next-generation architecture, which is 100-percent SystemVerilog, able to support UVM, OVM, and VMM, and surrounded by productivity tools including a completely new protocol aware debug environment.”
Note: Check out Janick Bergeron talking about Discovery VIP …