Please Join Us at SNUG Silicon Valley Next Week

Following a very successful DVCon in San Jose two weeks ago, next week we travel a few miles up the road to the Santa Clara Convention Center for the Synopsys Users Group (SNUG) Silicon Valley event. This will be our third year in a row exhibiting at this show, and it has become one of our favorites. We will also be speaking for the first time ever, and we’ll fill in all the details shortly. But let’s start by looking at why this show stands out and why we enjoy it so much.

SNUG actually has quite an interesting history. It began in 1991 as a way for Synopsys users to discuss common problems and solutions, meet with technical experts from the company’s R&D and AE teams, and learn about new products and features. Unlike many single-vendor conferences, SNUG has been driven largely by the users. They choose the papers to be presented and make many of the key decisions on how the event is run. Synopsys of course provides support in many ways.

When we first attended in 2013, we were worried that we would not find many verification engineers attending. Synopsys, after all, has its roots in electronic design (Design Compiler) and designers as its users. Although the company has also had verification products for many years, its marketing has never quite caught up. The SNUG exhibition is called “The Designer Community Expo” (DCE) and the SNUG site includes the following phrases:

• “design ecosystem partners”
• “members of your local design community”
• “users of Synopsys design tools and technology”
• “real-world design challenges”
• “largest community of design engineers in the world”

We’re teasing Synopsys a bit here, since as we’ve noted before the industry terms “electronic design automation” (EDA) and “Design Automation Conference” (DAC) are similarly limited. But we found a considerable contingent of verification engineers at SNUG, many of them receptive to our message that new solutions are needed in the SoC era. This has not been the case at some of the other single-vendor events we have attended, so our thanks to Synopsys and the SNUG team for drawing verification users.

According to Synopsys, today there are “13 SNUG conferences worldwide drawing nearly 10,000 tool users, representing more than 900 companies.” That’s impressive by anyone’s standards. In addition to Silicon Valley, last year we exhibited at SNUG Boston and Austin, meeting even more verification engineers looking for new ideas. And we have a lot of new ideas: a month ago we published a blog post on how the Breker Trek tools connect with Synopsys products at six intersection points:

• Simulating our automatically generated test cases in Synopsys VCS
• Connecting to Synopsys VC verification IP (VIP) models in the testbench
• Verifying designs that include Synopsys DesignWare library design IP
• Automatically generating C test cases to run on DesignWare ARC processors
• Integrating tightly with Verdi and Verdi HW SW for a unified debug flow
• Exporting system-level coverage to Verdi and Verification Planner

We’ll be demonstrating many of these connections at the SNUG DCE, held Monday, March 23, from 4:00 pm until 8:00 pm. We will also be delivering a talk on “Integration of Portable Test Cases and System-Level Coverage with Verdi HW SW Debug Using VC Apps” in the VC Apps Developer Forum session on Tuesday, March 24, from 10:30 am until noon. It is unusual for another EDA vendor to speak at SNUG, and we thank Synopsys for providing this opportunity.

There are many other sessions of value for verification engineers at SNUG Silicon Valley over three full days (Monday, March 23 – Wednesday, March 25). Be sure to check out the complete schedule so you don’t miss any topics of interest. We invite you to listen to our Verdi integration talk and to stop by our booth to say hello and to learn more about how we work with Synopsys tools. We’re really looking forward to next week; see you there!

Tom A.

The truth is out there … sometimes it’s in a blog.

Tags: Accellera, Breker, DCE, debug, design IP, EDA, functional verification, graph, graph-based, HW SW, portable stimulus, Santa Clara, scenario model, simulation, SNUG, SoC verification, test generation, Universal Verification Methodology, uvm, VC Apps, VCS, Verdi, verification IP, VIP

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