The Breker Trekker
Tom Anderson, VP of Marketing
Tom Anderson is vice president of Marketing for Breker Verification Systems. He previously served as Product Management Group Director for Advanced Verification Solutions at Cadence, Technical Marketing Director in the Verification Group at Synopsys and Vice President of Applications Engineering at … More »
Six Points of Connectivity with the Synopsys Verification Flow
February 18th, 2015 by Tom Anderson, VP of Marketing
In any industry dominated by a few large companies, it is important for the smaller players to ensure that their products work well with the broader solutions from the majors. Recognizing this need, and sometimes encouraged by legal action, the large companies develop partnership programs to enable and even foster integration with their solutions. All this is true for the EDA business, where the “Big 3″ work closely with many smaller vendors for the sake of their mutual customers.
In Breker’s case, we generate SoC test cases that run on a variety of software and hardware platforms. We do not build any of those platforms ourselves but we need to verify that our test cases can run properly on them. Accordingly, we are members of several important partnership programs and we work closely with other vendors to find and fix any interoperability issues before our customers run into them. In this week’s post, we focus on how we work with Synopsys, the EDA market leader.
We’ve been a member of the Synopsys in-Sync program for several years, with the initial focus on ensuring that their VCS simulator would run our test cases generated by our TrekSoC. We have made lightweight use of the various simulator APIs and so we rarely have any problems with anyone’s simulator. However, having VCS available in-house means that we can quickly debug any future interoperability issue that might arise. Proactively using VCS for our own regression tests greatly reduces the chance of any such issue ever making it to a customer.
Running our test cases, both compiled C code and testbench transactions, in VCS is the first of six points of integration that we will discuss in this post. Most of the time VCS is running a testbench complaint with the Accellera Universal Verification Methodology (UVM) standard, and the testbench connects to the interfaces on the design being verified using UVM-compliant verification IP (VIP). We provide a run-time module called TrekBox that connects to the VIP models, controls their activities, and synchronizes it all with the compiled C code running on the processors.
Synopsys is an industry-leading provider of VIP, including titles for standard protocols such as Ethernet, USB, and PCI Express. We’ve encountered Synopsys VC VIP in numerous customer engagements and have found them easy to use, easy to connect, well documented, and truly compliant with the UVM. Simulation with testbenches containing Synopsys VIP is the second point of connectivity for the Breker products.
Synopsys is also an industry leader in design IP, also known as implementation IP. The DesignWare library includes controllers for many of the same protocols supported by the VC VIP. We often see customers using DesignWare as part of the design they’re simulating and verifying. Design reuse is absolutely essential for today’s large chip designs, and we’re pleased to be able to work well with the Synopsys IP for a fast simulation solution.
When we generate C test cases for software-driven verification, we produce generic C code so that we can run on any processor with a C compiler. Sometimes, our tests run on one or more DesignWare ARC processors within the SoC. That works just fine, extending the third point of connectivity between the two companies. But simulation involves more than just the simulator, the testbench, and the design being verified. A comprehensive debug solution is required in order to diagnose and fix any design bugs uncovered by the test cases.
Synopsys provides the Verdi Automated Debug Solution to view source code, waveforms, and other verification information in one convenient product. For software-driven verification, Verdi HW SW Debug is an essential extension to view assembly code, processor state, and other critical debug information. Through the integration available with the VC Apps Exchange, displays from our TrekBox run-time module can be displayed within Verdi HW SW Debug, and all windows remain synchronized.
The Verdi capabilities also include rolling up all forms of coverage into a single consolidated view of verification status. The Breker Trek suite of tools generates and tracks high-level system coverage metrics such as which use cases have been exercised and which tasks have been executed in parallel. TrekBox can export our coverage as SystemVerilog cover groups that can be included in the Verdi roll-up. The following diagram summarizes the first five points of connectivity described in this post.
Finally, the import of Breker’s coverage metrics also means that coverage targets identified in Verification Planner can be satisfied by the TrekSoC test cases, with credit given in the original verification plan. This is the sixth point of our integration with the Synopsys verification flow but it surely will not be our last. Additional projects underway or planned will be discussed in this blog when results are available.
Note that SNUG Silicon Valley, including the VC Apps Developers Conference, will be held March 23-25 at the Santa Clara Convention Center. Breker will be there, and we’ll talk about our plans as part of the lead-up to this event. In the meantime, we have a brand-new white paper on our integration with Synopsys, with more details than we could fit in this post. You can request it by clicking on the link below.
The truth is out there … sometimes it’s in a blog.
Tags: Accellera, Breker, debug, design IP, EDA, functional verification, graph, graph-based, HW SW, portable stimulus, scenario model, simulation, SNUG, SoC verification, test generation, Universal Verification Methodology, uvm, VC Apps, VCS, Verdi, verification IP, VIP