Breker and Carbon Team Up to Provide Fast, Accurate SoC Verification

This morning, our good friends at Carbon Design Systems announced a new Web portal to provide system-level solutions for system-on-chip (SoC) developers. The Carbon System Exchange provides a wide range of Carbon Performance Analysis Kits (CPAKs), pre-built systems or subsystems with software at the bare metal or operating system level. CPAKs are key building blocks for SoC teams creating complete virtual prototypes for their designs.

Breker is one of nine announced IP and EDA partners who are working with Carbon to create new CPAKs or enhance current offerings. Some partners, such as ARM, Arteris, and Cadence, are providing processor models or other forms of IP commonly found in SoCs. Others, such as Kozio and Breker, are providing software to run on the CPAKs. As you might expect, what we’re actually providing is not a fixed set of software, but rather the ability for CPAK users to generate multi-processor, multi-threaded, self-verifying C test cases.

Specifically, we are partnering with Carbon to deliver processor-based CPAKs, a graph-based scenario model representing the CPAK, and a bundled copy of our TrekSoC solution. We talked a couple of weeks ago about our new applications (“apps”) strategy, in which we provide scenario models to tackle specific verification problems. You can think of this partnership delivering an additional app for each CPAK bundled with TrekSoC. You can immediately generate test cases to run on the chosen system or subsystem model.

For example, our first offering builds on Carbon’s Cortex A15 CPAK, which features the four-core ARM Cortex-A15 processor. The scenario model that ships with our version of the CPAK generates complex four-processor test cases “out of the box.” This level of activity stresses the model enough that you can make performance measurements and identify possible bottlenecks. Carbon phrases this well: “Users can optimize the system using multiple benchmarks for performance exploration, combining realistic system traffic to understand cache statistics, memory throughput and latency, and validate assumptions made during the design process under various workloads.”

Of course, SoC designers add lots of their functionality on top of the processor subsystem. Breker’s graph-based scenario model is easily extensible so that you can capture aspects of the design and the verification space beyond what’s modeled in the CPAK. The generated testcases continue to stress every aspect of the design. If you add any SoC components that must be partially or entirely coherent with the processor subsystem, TrekSoC’s ability to verify cache coherency is enormously valuable.

Every CPAK that we provide on the Carbon System Exchange fits within the overall Breker verification flow. TrekSoC generates test cases for your complete SoC in virtual prototypes and in RTL simulation. If you want to extend beyond the simulation domain into hardware platforms, TrekSoC-Si can generate appropriate test cases for emulations, FPGA prototypes, and actual silicon running in the lab. The same scenario models support architectural exploration, hardware verification, and post-silicon validation.

We are very excited to be working with Carbon and we believe that our collaboration on CPAKs will be of great benefit to our customers. If you want to try out graph-based verification, you will have a great starting point for a major subsystem of your SoC. If you’re already a Carbon customer, with virtually no effort you can supplement your existing software tests with TrekSoC’s automatically generated multi-threaded test cases. We’d love to hear any thoughts you have on additional CPAKs we should support.

Tom A.

The truth is out there … sometimes it’s in a blog.

Tags: ARM, Breker, Carbon, coherency, coverage, CPAK, EDA, functional verification, graph, performance, scenario model, SoC verification, TrekSoC, TrekSoC-Si, use cases

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