S3 Tutorial: SAR ADC, Node2Node, IP Integration, Analog with a ‘ue’

Several weeks ago, I had a chance to speak by phone with the folks of S3, a multinational IP vendor and engineering company headquartered in Dublin, Ireland. Darren Hobbs, Director of Product Strategy for the Silicon Business Unit, was on the call, as was Dermot Barry, Vice President of the Silicon Business Unit.

Our conversation centered on two topics: a new ADC just released by S3, and my hypothetical design project, the Dick Tracy keychain. It was morning in California when we spoke, but closing in on dinner time in Ireland. Hobbs and Barry were patient with my questions, nonetheless.

Per Hobbs, “We want to talk today about our latest product, a high-speed ADC and one of the most efficient [in the marketplace]. This announcement has produced a lot of headlines, but we want to drill into what it all really means. The specs we are using here is performance per milliwatt. We harp on that, because it’s really critical today. Typically, what’s said with a launch like this is that it [processes so many bits at a particular speed], but that doesn’t really indicate the performance of an ADC.

“What we’re doing here is putting our necks on the line by saying instead what our efficiency is – a very, very small ADC when manufactured at 40 nanometers, just .09 square millimeters, and only consuming 6 milliwatts of power. It’s efficient in the order of 31 femtojoules [10^-15 joules], which means for handsets that use 802.11ac, you get very high energy efficiency.”

Hobbs noted, “The biggest problem with smart phones today is the battery life. For instance, the iPhone 5 sucks out power in 5 or 6 hours. In the SoC and consumer areas, where the key metric is efficiency, the more you can carve off the silicon, the better. Translated into a consumer’s point of view, [with our new, smaller ADC] they will get an extra 6 or 7 minutes download time.”

“So,” I asked, “we’re bragging here about a few extra minutes of download time on a smart phone?”

“Yes!” Hobbs said emphatically.

“What’s different in your new design that’s allowed for this breakthrough?” I asked.

Hobbs said, “The SAR [successive approximation register] architecture. It’s been around for a while, but this is the first time someone has actually used it commercially. It’s allowed us to come up with a lot smaller, far more efficient ADC. The old architecture, the pipeline architecture, was okay for certain infrastructures that were all about speed, but with the SAR architecture, you get performance efficiency and speed.”

“Who designed your new product?” I asked.

“We’ve got a team of ADC designers who have been with us for a number of years, and designing high-speed ADCs for the last 15 years,” Hobbs said. “Previously they used a pipeline architecture, but with this latest generation they are using SAR.”

“What’s been tweaked in the SAR architecture to allow for these improvements?” I asked.

Hobbs said, “Within the SAR architecture, that’s a trade secret.”

“Speaking of secrets,” I said, “I’m working on a hypothetical wearable device – a ‘Dick Tracy’ keychain – but am having problems getting people to reveal the prices of their IP blocks. What does your new ADC cost?”

Hobbs said, “To be honest, that’s not something we share. It’s an IP block, so the actual price depends.”

“How far along in my purchasing discussion with S3 do I have to be,” I chuckled, “before you can tell me the price?”

Hobbs said he could give me a ballpark figure now: “The IP we sell can be anything from nuts to bolts, and can cost anywhere from $50,000 to $300,000. Again, it depends.”

“Should I be willing to spend tens of thousands, or even hundreds of thousands of dollars,” I asked, “just to put an additional 5 or 6 minutes of download time into my device?”

Hobbs responded, “Absolutely! Anything that can get you an extra few minutes is worthwhile. I’ve worked in the handset space myself, and getting [additional minutes is very important].”

“Let me put it this way,” Hobbs laughed. “From an operator’s [point of view], every minute a phone is active is another minute they can screw the consumer even more. So everybody wins!”

I also laughed, and then asked, “Why now and not last year, or even earlier, for your new ADC?”

Hobbs said, “It’s been done for the technology node. The node of choice at this moment is 40 nanometers and below, and that’s the node that makes sense, because this architecture uses quite a lot of digital logic, something which would have been difficult at 65 nanometers or above. So even 2 or 3 years ago, this wouldn’t have made sense.”

“Moving to the next lower node has been a major motivation?” I asked.

Hobbs said, “Yeah, this is the absolute reason, and we’re thrilled with the results. The beauty of the SAR architecture is, the smaller the node the faster the ADC. [Historically], mixed-signal designs have trailed digital designs by several nodes, but with this new design we are already working on plans to go to 20 nanometers.”

“Do you ever recommend a target node for your customers?” I asked.

Hobbs said, “Typically, we’re not in that position of power with our customers – although, if we were ARM we would be – so in general, we need to adapt to what the market’s looking for. Certainly at this point, 40 nanometers is still popular in Asia, although 28 nanometers is becoming more popular with western Tier 1 vendors.”

“Is it a nightmare trying to keep pace with your customers’ moves to the next node?” I asked.

Hobbs said, “It can be tough on our resources, quite tedious, but the SAR architecture is very easy to port between nodes.”

Turning to another topic, I asked, “Given the signal speeds available in digital devices, why do I really need to have any analog in my design at all? Why can’t I just simulate analog with high-speed digital signals on-chip?”

“First of all, I would be out a job,” Hobbs laughed. “But, in fact, you’re always going to need some analog, even if today it’s being pushed to the peripheral of the design. [You can’t just rely] on a high-speed wire lines, because you’ve got real-world effects. Instead of just transmitting 1s and 0s, you get a big wash of stuff with analog.

“You’re always going to need a certain analog converter to look at what’s coming out the other end, and you’re never going to be able to get rid of the converter at the front end. It’s a lot more tolerant to noise [than] digital.”

“Okay, so who are you going up against? Who’s your competition in this area?” I asked.

Hobbs said, “If you look at Design-and-Reuse or ChipEstimate, you’ll find a lot of mixed-signal and ADC converters out there. But Cadence and Synopsys, those are the two big ones today.”

“Do you ever find it annoying that your vendors are competing with you?” I asked.

Hobbs said, “It’s a funny relationship. We find our EDA vendors have trouble selling IP. Their sales guys are used to selling CAD tools, but selling IP blocks is different. You don’t get the same value for IP. It can be a tougher sell and quite nebulous, so our vendors are having [difficulties there].”

Again referencing my Dick Tracy keychain, I asked, “How much design help are you willing to throw in for free, if I purchase IP blocks from you for my project?”

Hobbs said, “That’s actually one of our differentiators at S3. There’s an S3 group with a mixed-signal portfolio, and then there’s our solutions side. We combine both at S3, which makes us unique. [Having said that], just like with the price of a block of IP, the amount of free design help we’re willing to offer an IP customer depends.”

Another voice chimed in on the phone call: “May I jump in? I’m Dermot Barry, Vice President for the Silicon Business Unit. To answer your question, this is what differentiates us from the EDA guys.

“The EDA guys have a IP business that has to fit inside of their traditional tool business, where the tool business is recognized as a high-gross market. Their IP business is an add-on – yes, a significant add-on going forward – but it can’t result in a diminution of their overall growth margin today, or their investors won’t like what they see.”

“That means to a large degree,” Barry continued, “the EDA guys are very unwilling to do customizing, to provide customized IP blocks. Yes, they’re developing IP blocks just like the rest of us, but they’re developing them on the hope that their [standard] blocks will meet customer requirements for upcoming products. Typically, the EDA guys shy away from doing customization.”

Barry added, “Whereas, with our SAR ADC, we have an outline of performance, but it can be modified. We can make those modifications – there is some extra cost on the license fee for doing so – and also provide integration support, so what we deliver to our customers is a set of views and integrations guidelines.”

Barry said S3 has a lot of experience in this area: “We’ve been doing IP integration for over 20 years – our own IP, plus legacy IP from third-party suppliers like ARM and MIPS. We understand what’s required in terms of integration guidelines.

“When we deliver a block to a customer, we say: ‘Here’s what we recommend in terms of do’s and don’ts in placing this IP block in your design.’ We’ll do a floorplan review with customers, plus give suggestions as to whether that block placement could potentially lead to performance problems within the system.

“When we review the customer’s layout, we also ask if they have followed our guidelines. In fact, sometimes customers don’t even follow their own guidelines, so it’s in our interest to pick up on problems before they tapeout their design. After tapeout, it’s just too late. For us, a satisfied customer is one that uses our IP in their design and meets their design objectives.”

“The integration of IP into a project is a real problem?” I asked.

Barry said, “Certainly that is true for a large portion of our customers, but there are also many customers who are very savvy, the Tier 1 IDMs and fabless companies in the top 10. These guys have seen a lot and have detailed processes in place for integration.

“They know, when taking a bunch of IP from different suppliers, including from their own internal groups, that it’s not a slam dunk to put it together. It has to be done in a very controlled manner. For those customers, it’s hard to sell them on our integration expertise. They just want to an IP vendor who provides quality in terms of the deliverables.

“But for the guys who are  Tier 2 semiconductor companies, or even for many system and products companies, they don’t do as many leading-edge designs and often don’t have the capability. Those [types of] customers really benefit from our expertise, although oftentimes they need to have a failure in order to recognize that they didn’t fully understand what they were getting into when integrating IP into a design.”

“Does that include not recognizing the difficulties of porting designs from one node down to the next?” I asked.

Barry said, “Again, it depends on what kind of customer. For Tier 1 customers, porting designs is not an issue, particularly at more mature nodes like 40 nanometers. For leading-edge nodes like 16, however, the costs of mask sets [means fewer customers are working there].”

Hobbs added, “Today, you’ve got some very large semiconductor companies who can afford to go to 16 nanometers. But even for them, it’s only for a small portion of their product portfolio. What we’re seeing with many other customers, however, is guys coming from 65 nanometers and moving to 40. We have to do some hand holding for those customers, but that can be an opportunity for us as IP providers to also engage as design service providers.”

“Meanwhile,” Hobbs said, “there are still a lot of designs – analog designs for wireless radios or satellite radios, stuff like that – that are being done at .18 or .13 nanometers, process nodes that are more than sufficient [to meet the needs of those designs].”

Wrapping up our lengthy call so Barry and Hobbs could get some dinner, I asked “Given that you guys live on the wrong side of the Atlantic, how do you actually spell analog?”

Hobbs laughed and admitted, “Sorry, but we’ve been raised to spell analogue with a ue.”

********************
More on S3 …

S3 Group, headquartered in Dublin, has development centers and sales offices in San Jose, Philadelphia, Portugal, Poland, the Czech Republic, Holland and Singapore.

Per the website: “S3 delivers IP and tailored silicon solutions to semiconductor vendors, OEMs and service operators. The company is the longest-serving independent silicon solutions provider in the industry, building a wealth of experience and engineering expertise over the last 28 years. The company provides a comprehensive portfolio of RF and mixed-signal IP, in addition to design services.”

********************

Tags: ADC, ChipEstimate, Darren Hobbs, Dermot Barry, Design-and-Reuse, S3 Group, SAR ADC, SAR architecture, successive approximation register architecture

This entry was posted on Thursday, April 10th, 2014 at 8:46 pm. You can follow any responses to this entry through the RSS 2.0 feed. You can leave a response, or trackback from your own site.