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Ty Garibay
Ty Garibay
Ty Garibay is the Chair of the IP Track for DAC 2018 and CTO of Arteris IP, a provider of interconnect IP for SoCs. Previously, Ty led design teams at Altera, Texas Instruments and ARM. As an architect, he has led the development of MIPS, ARM, x86 and 68K microprocessors. Ty is named on more … More »

#55DAC #5: Must-see New Deep Learning Processors, Embedded FPGA Technologies, and SoC Design Solutions in the DAC 2018 IP Track

 
May 9th, 2018 by Ty Garibay

Some of the most valuable events at DAC are the IP Track sessions, which give small- and medium-sized companies a chance to share innovations that might not get much attention elsewhere.

The use of IP in SoCs has exploded in recent years. In a panel at DAC 2017, an industry expert noted that the IP market was clearly growing even faster than EDA itself, due to the fact that more and more chip makers are externalizing IP development functions.  This is similar to what happened with EDA tools in the 1990s.  The externalization trend is ongoing, and there is still more IP to be go. With continued advances in semiconductor processing, new systems-on-chip (SoCs) are always increasing in complexity.  Research firms estimate that some SoCs include up to 200 blocks of IP, licensed from multiple companies, ranging from an I/O cell all the way up to an Arm CPU. Identifying and acquiring or designing all of the IP blocks is just the beginning.  The big challenge is when you have to bring all of that IP into one design database and manage the versioning and design flow requirements of each unique block.

So, if you’re working to optimize your designs with IP, come check out the DAC IP track this year.  Most of our sessions consist of invited presentations and panels. We have nine 90-minute sessions total, from Monday through Wednesday of DAC week. Five of the sessions are for invited presentations—three 30-minute presentations each—and two for panels. The final two sessions will showcase submitted and reviewed presentations from industry and academia.  This year, the submissions seem to reflect the increased interest in IP-based design, as we received 25 percent more than we did last year.

One area that is hot across DAC this year is machine learning, perhaps no surprise given how much artificial intelligence and machine learning technology is proliferating in systems and in the media.  We have an IP for Machine Learning session that will be fascinating. Cambricon, an up-and-coming Chinese company, has created the first AI deep learning IP in the world. On Monday morning, they will present the details of their deep learning processor. In the same session, you’ll hear from Cadence, which has developed a neural processor based on its Tensilica architecture, and Dr. Vivienne Sze from MIT, who will discuss the types of hardware that are required for deep learning.

The IP track also includes two panels—one of which focuses on the perennially “hot” topic of low power. Industry editor John Blyler will moderate a panel that includes representatives from companies including TSMC, Microsoft and Minima, for  a wide-ranging discussion of the latest problems in achieving low power for new applications such as virtual reality wearables, IoT devices and even automotive systems.

The IP Track sessions are also a good opportunity for engineers to learn about some types of IP that most have not gotten a lot of exposure to yet. We have an excellent session on embedded FPGA that includes presentations from some of the leaders in this new market: Achronix, Flex Logix and Menta. They will talk about three very different ways of implementing FPGA as an IP which can be instantiated into an SoC, as opposed to the other way around (like Xilinx’s Zynq or Intel/Altera’s SoC FPGA line). Embedded FPGAs used to be a tough sell because FPGAs traditionally required a great deal of area, but eFPGA vendors are getting traction now with these new offerings which are purpose-built products for embedding in SoCs, rather than being derived from existing full chip FPGAs. I’m interested to find out what has made it possible for these vendors to go from “it’ll never work” to “yes, we have customers.” In fact, Flex Logix will have Sandia Labs, a customer, co-present and describe the end application which takes advantage of the reprogrammability of the eFPGA.

Another session I’m personally interested in deals with IP to support CMOS image sensors (CIS). The CIS market is exploding, and image sensors are being integrated in SoCs for multiple applications, including automotive. These new image sensor IPs require new architectures and also innovative mixed-signal design. Chronocam, Austria Micro Systems and Forza Silicon will each present their solutions in this space on Tuesday morning.

At the conference this year, we have an excellent mix of EDA, IP, SoC, and foundry process engineers who will talk about how our industry is changing. This is going to be a great year for DAC. The event is back in San Francisco again this year, so it’s an easy hop from Silicon Valley, just grab the bus and come on up!  I look forward to seeing you in June in San Francisco (June 24-28)!   Register today for the Designer and IP track badge. 

#55DAC: Must-see DAC technical sessions this June in San Francisco

 
April 26th, 2018 by Valeria Bertacco

By Valeria Bertacco, 55th DAC Conference Program Chair

This June at DAC, we will have the opportunity to discuss and learn about key topics that are emerging in the system design and automation community.

To start, we have the challenge of designing at the end of silicon scaling and beyond: devices, design complexity and verification. On Monday, there will be a tutorial on designing at advanced technology nodes, followed by an invited session on the same topic on Tuesday in the Designer Track.

We will also begin to discuss modern challenges in verification in the face of today’s design complexities. This hot topic will pick up throughout the week with panels, special sessions and reviewed paper presentations, ranging from automating away the complexity of the design process (“the road to no human in the loop” on Tuesday), design productivity (“design productivity in SoC,”  “mind the gap”), verification challenges (“black art of verification”) and new emerging devices (“the zoo of emerging devices”) to design tomorrow’s computing systems.

For those of you  interested in emerging storage and storage technologies, there is also abundant coverage:  From solid-state storage devices (“how solid is your storage,” “solid ideas”), to the storage-centric system solutions (“memory-centric architectures,” “emerging storage,” “memory that never forgets”), complemented by a thorough discussion of the leeway of approximation techniques, in particular in relation to their impact on storage, system reliability and application accuracy (“watch your bits,” “good enough is enough”).

For the researchers, both from industry and academia, we will have a two-hours panel on research funding. Wednesday after lunch we can discuss trends and directions in funding with a slate of panelists from around the globe. This topic is becoming a strong DAC tradition, in light of the interest it has attracted in the recent past.

Moreover, this year at DAC we will begin the conversation about diversity in our industry: what is its value, how do we attain a diverse work environment and what changes do we need to pursue for it to be effective. This discussion will start with an all-day Monday tutorial and will continue with a panel on Wednesday afternoon (“making your team high performing,” “diverse engineering teams are better”).

And then, we have of course the two topics that have been gaining the strongest momentum in the past few DAC events: security and deep learning. On the security front, the program offers two tutorials on “IoT security” and “verification for security.” Once we have built the background knowledge, the program offers multiple sessions each day, discussing software and hardware security, ranging from “best practices” in the designer track, to innovative solutions, both at the architectural and logic levels, in the context of general and embedded systems, particularly the highly exposed IoT world.

As you probably guessed, deep learning is pervasive throughout the program, and I cannot even begin to list all the sessions that tackle this topic. Just know that we will offer several research presentations, invited sessions and panels, both in the research and designer/IP tracks, presenting how to design for deep learning application systems, and how to leverage deep learning in our design processes; deep learning for security and security in deep learning applications. If you are not a deep learning expert, I strongly recommend the broad offering of tutorials (“ML for EDA,” “ML in IoT,” “data science for verification”) to get you up to speed by Monday night.

As you can see, it’s a packed conference program! I hope you will enjoy it, and find some time for the always important networking, too — at the sessions or at the research lounge. I will be there, walking the hallways and attending the talks, and I am very much looking forward to reconnect with old friends and meet the new faces of DAC!

DVCon – Bigger and Better!

 
January 19th, 2018 by Dennis Brophy

Bigger and Better applies to DVCon U.S. 2018, but the fact is the electronic systems you design and verify grow bigger and better every year as well.  It is no accident that DVCon U.S. has grown, too to keep pace with you!   I am happy to share many of the details of additions we have made to DVCon U.S. to add topics of importance that are motivated by the designs you are working on today and the systems you are creating for tomorrow.  We have been with you at the start of the smartphone, PC and tablet era and are with you now as new huge market potentials are on the horizon for the Internet of Things (IoT), wearable systems and intelligent embedded systems that are on a path to support fully autonomous vehicles.

From Humble Beginnings

We have seen a lot together as DVCon U.S. celebrates its 30th birthday milestone this year!  The first VHDL Users Group meeting was held at the 1988 Design Automation Conference in Anaheim, CA USA during a birds-of-a-feather session.  From there it has grown to be known as DVCon now being held in the United States, Europe, India and China.  After that 1988 meeting, VHDL was joined by Verilog with promotion arms created for both languages.  A language war was presided over and peace in a bilingual/multilingual world was embraced.  From a small start, a panoply of DVCons now reach thousands of practicing design and verification engineers around the world annually.  It is humbling to be part of this growth and success and even more humbling to help all design and verification engineers be that much more productive and successful.

Having been in the industry in 1988, I do recall the planning that went into the 1988 meeting, but, personally, I have no memory of attending it.  If you were there in the beginning or perhaps “not yet born” or “barely out of diapers” as would be the case with younger attendees, I can assure you that this event continues to bring users together to raise awareness of design and verification challenges and share solutions from fellow engineers and tool suppliers.  It is this exchange of information that brings attendees back year after year.  DVCon U.S. 2018 is a highly informative and educational event we hope you will attend.

Conference Highlights

As General Chair, I am privileged to represent the work of the Steering Committee and Technical Program Committee members.   They do most of the work to form the conference content with help from our conference management company, MP Associates.  The following are highlights for this year.

Keynote: Christopher Tice, vice president of Verification Continuum Solutions in the Verification Group at Synopsys will deliver this year’s keynote, “Industry’s Next Challenge: The Petacycle Challenge.”  This is the first time Mr. Tice will address DVCon.  Mr. Tice is a longstanding and respected industry executive who has a focus to drive solutions in fast-growing verticals such as automotive, networking and IoT.  Mr. Tice greatly complements this year’s program content and the future we look forward to creating.

Tutorials & Short Workshops: Of the four days of DVCon, the first and last day offer tutorials.  New for this year are Short Workshops on the fourth day.  The first day of tutorials is colloquially referred to as Accellera Day.   This year Accellera sponsors a morning and afternoon tutorial.  The morning tutorial will cover its emerging Portable Test and Stimulus standard and the afternoon will focus on the popular Universal Verification Methodology (UVM) and the work Accellera has done to complete its IEEE-1800.2™-2017 (the IEEE name for UVM) compatible reference implementation.  On the fourth day of the conference, there will be six tutorials with a large focus in the afternoon on design and verification targeted at autonomous automobiles and the impact of functional safety requirements on those systems.  Are there any bets on when and who will be the first person to come to DVCon in a fully autonomous vehicle?

We added the Short Workshop concept to draw more topics to provide attendees more opportunities to join in discussions and learning exercises that would not be as long and comprehensive as full tutorials.  The four Short Workshops on Thursday include topics on Deep Learning for the Design & Verification Engineer, Formal Verification, Mutation Coverage for Advanced Bug Hunting and one that will seek to have the design and verification engineer focus on getting the job done without concern that underlying it all is formal technology.

Technical Papers and Posters: From novice to expert, you are covered.  Design and verification practitioners are set to cover popular topics in the formal paper presentation sessions and the ever popular poster sessions.  The topics covered include UVM, functional and formal verification, high-level synthesis, C/C++/SystemC, assertion based verification, Portable Stimulus, safety critical verification and ISO 26262 fault analysis, advances in low-power design and verification.  The RISC-V processor core even makes an appearance with a paper on its UVM-based verification model.  You will certainly find something in the program that will help in your daily design and verification activities.  You get to vote on best paper and poster awards to recognize the best-of DVCon.  Authors are greatly appreciative of the recognition.  This year we have shared some best practices for presenters on how they can deliver better presentations.  We hope this shows.  If this works, we may have made your job to discern the best paper and best poster just that much more difficult.

Panel Discussions: We have two panels this year, and both will be on the third day of the conference.  The first panel reflects the issue that has come with the advent of large designs: Big Data.  The more and more verification information that is generated, the harder it is to find root causes to problems or system flaws.  With so much information being generated, you may find it hard to attain the system coverage you seek.  The panel will be a good way for industry experts to explore this more.  The second panel will explore the right tool for the hardest verification jobs.  This reminds me of the old adage that says “if all you have is a hammer, everything looks like a nail.”  The good news for design and verification engineers is that there are many tools to choose from and the panel should help us understand which tool is best for which task.  And for both panels, we will be ready and open for questions from the floor.  This is your time to speak too!

Exhibits: We have just about every inch of exhibit space covered.  This makes for exciting social interactions after the conference program ends, during the evening receptions or during breaks.  It is a good venue for business meet-ups when the conference is in session.  You will find the latest in EDA tools, design and verification IP and services represented.  Armed with what you have learned in the conference setting, the exhibitors will be ready to share their advances that might help you with many of your pressing design and verification issues.  Whether you are in the exhibit area or connecting with peers at the hosted lunches, you will have many opportunities to network with your peers and learn from each other.

Thank You

On behalf of the DVCon U.S. 2018 Steering Committee and Technical Program Committee, I want to thank the hundreds, if not thousands of those who worked on or supported prior conferences from 1988 until today.  It is their hard work and dedication that sets the stage for all of us now.  I want to acknowledge the ongoing support of conference sponsors and Accellera Systems Initiative for their financial backing.

As you make your way to DVCon U.S. 2018, our conference “front door” is managed by MP Associates who has been the conference committee’s back office the past year to bring this full program to you.  I want to thank them for all their work as well.

With that, I look forward to seeing many returning faces and meeting new attendees.  I offer each and everyone one of you a hearty welcome to DVCon U.S. 2018!  Let’s come and learn, exchange ideas and advance design and verification together.

To register for DVCon U.S. 2018 visit here.  Advance registration is available through January 26th.

#DAC55 3: Last Call for Designer and IP Track presentations for 2018 event in San Francisco

 
January 19th, 2018 by Sharon Hu - General Chair DAC55 and a professor in dept of CS and Engineering at Univ of Nortre Dame, Indiana

One of the most popular part of Design Automation Conference needs you! The Designer and IP tracks are open for submissions and you have until Jan. 23 to send in your abstracts.

These sessions are where industry experts discuss different tools, flows, and methodologies that will help you and your design team. In addition, they provide excellent opportunities for education and networking between end users and tool developers.

I’ve been to many of these sessions in recent years, and if attendance is any indication, they’ve become valuable parts of the DAC program. Mac McNamara, my predecessor as General Chair last year, compared design to putting socks on a chicken, but I can say from sitting in on several sessions that it can be done!

The Designer and IP track presentations are intended to be free of marketing and sales pitches and tuned to the needs of today’s designers. That’s a key reason they’ve become so popular. Not only will your work receive a lot of attention from fellow designers and tool users but the submission process is extremely easy.

All you need to do to is to submit a 100-word description of your presentation with six slides. Yes, you did read correctly – six slides and 100 words.  If it’s accepted you can begin to educate the 2018 attendees how to put socks on those chickens!

This year’s Designer Track and IP Track will include presentations, poster sessions and a rich set of invited talks/panels for information exchange and interactions.

The DAC Designer Track brings together IC designers, embedded software and system developers, automotive electronics engineers, security experts, engineering managers, and verification engineers from across the globe. Past presenters have included AMD, ARM, Bosch, BMW, Cadence, Delphi, GM, and more.

Leading the Designer track committee is Chair Zhuo Li from Cadence. Zhuo has been a member of the DAC Executive Committee for several years and has experience in leading the Designer Track program.  Zhuo is joined by designer track Vice Chairs Robert Oshana from Qualcomm/NXP and Renu Mehra from Synopsys. Rounding out the excellent team are subcommittee chairs that come from companies such as Global Foundries, AMD, Intel, NXP and Analog Devices. A complete list can be found here.

The IP track this year is chaired by Ty Garbere, here in the Silicon Valley. Ty is new to the Executive Committee but not new to IP.  Ty and his team stretches from the Austin, Texas, to the Bay Area to Marseille, France (see all the names and affiliations here).

As part of our outreach to attendees for these tracks, we like to say there is no better way to improve your “Design and IP IQ” in such a short amount of time. To help improve that IQ, submit your proposed presentations today! And remember to visit the dac.com for updates as we head into the final months of planning for 2018.

#55DAC 2: Teams tackle deep learning in DAC design contest

 
December 13th, 2017 by Sharon Hu - General Chair DAC55 and a professor in dept of CS and Engineering at Univ of Nortre Dame, Indiana

When it comes to tackling leading-edge design challenges in fun ways, there’s no better place than DAC. For DAC 2018, we’ve created a System Design Contest targeting machine learning on embedded hardware.

If you think this is too leading edge for a design contest, you’d be mistaken: More than 100 teams registered for the contest. You can find a full list of the teams here: http://www.cse.cuhk.edu.hk/~byu/2018-DAC-HDC/teams.html

So how does the contest work:

Teams had the choice of using a Xilinx PynQ-Z1 FPGA-based development system or an NVIDIA Jetson TX2 development system, as well as software and deep-learning tools kits. Xilinx and NVIDIA donated boards to support the efforts.

Drone maker DJI donated a data-set that included more than 100 video clips with full annotation of the bounding box for the tracking object (a person or car).

The teams built either FPGA- or GPU-based systems to track people and vehicles from consumer drones using deep learning methods running on advanced embedded systems platforms. A hidden dataset is used to evaluate the performance of the designs in terms of accuracy and power consumption.

Read the rest of #55DAC 2: Teams tackle deep learning in DAC design contest

Introducing the 55th DAC General Chair – Dr. Sharon Hu

 
November 2nd, 2017 by Sharon Hu - General Chair DAC55 and a professor in dept of CS and Engineering at Univ of Nortre Dame, Indiana

My first time attending DAC was in 1991, and I am so excited to be serving as the General Chair for the 55th annual conference this June. Coming from academia and meeting new people in the industry sector who have been involved with DAC for years, I thought this to be good opportunity to introduce myself to the entire community.

I got my start in engineering as an undergraduate student. Both of my parents were engineers and encouraged me to pursue engineering as well. I studied electrical engineering and came to like it very much. Before making the jump into academia, I worked at the General Motors Research Labs for four years right after receiving my Ph.D. At that time, I was exposed to the emerging area of hardware-software co-design and really enjoyed it. Over time I began to realize that many factors in industry could constraint the choices of research projects that one can work on. When an opportunity came up, I decided to make the switch to academia. Currently, I am a computer engineering professor at the University of Norte Dame and love being able to work with students who are as interested in this field as much as I am. There is a drive for learning in these students, and I see the same passion when I attend DAC.

Now onto DAC 2018 and the task of being General Chair. We are a part of an industry that is changing and evolving, and DAC is a major part of the industry ecosystem and a large task for one person to manage as I have learned. Thankfully, I have been able to head a committee of people who are as passionate as I am. I’m proud to be working with such a talented and diverse group of volunteers from academia and industry that span many sectors including electronic design automation (EDA), design, embedded systems, intellectual property (IP) and semiconductors. You may be hearing from some of these folks over the next 10 months as we plan the overall program, so please take a look and welcome the 2018 Executive Committee (EC): https://dac.com/committees/executive.

The EC has a team building ritual during the first onsite planning meeting that is held each September. This year’s event was hosted by Cozy Meals in San Francisco.  It was a wonderful night of getting to know each other by cooking together and sharing our culinary experiences. As I hoped we would, this group enjoyed the evening and shared many stories and laughter.


There are a number of things that I really like about DAC, but towards the top of that list is the format of the conference. There aren’t many places where research, learning sessions, and exhibitions co-exist. DAC’s wide range allows me to hear cutting-edge research results on a diverse set of topics while being able to interact with friends and colleagues from all over the world.

And speaking of topics, I’m very excited to have worked with the EC in expanding DAC’s topic areas for 2018.  DAC has a perception in the industry to be an EDA software and chip design conference when in reality over the years DAC has grown its focus from chips to systems.  This year’s topics, which will be incorporated in all aspects of the conference, will focus on

  • Traditional EDA
  • Design
  • Automotive software
  • Embedded systems and software
  • Machine learning/AI
  • IP
  • Security/privacy

I encourage everyone to look closer at DAC’s call for contributions to understand how the conference has evolved over the past 55 years and see where you can be part of this expanding and educational event.  The call for contributions is now open and we are looking forward to receiving submissions for regular research papers, special sessions, panels, tutorials and workshops. The deadline is November 21.  Along with the research focused submissions, the Designer and IP Track submissions are open with a submission deadline of February 3, 2018.

As you can see, each year there are more opportunities to learn and keep up with the industry as it changes, this is another part of DAC that is so special. With the help of the EC, exhibitors, and attendees this year has the potential to be the best DAC yet.

#54DAC 9: Live from Austin: The DAC Exhibition floor; 3 Full-days of Activities

 
May 30th, 2017 by Michael (Mac) McNamara, Gen Chair 54th DAC; Pres & CEO Adapt-IP

I’ve been attending DAC since 1992, and it’s astonishing to me how each new year brings more and more compelling experiences for attendees. Of course DAC is rooted in a world-class IEEE and ACM sponsored conference program, but the activities in the exhibit hall just get more and more amazing and fun every June.

The exhibit hall at this year’s DAC is not just a place where exhibitors from around the world will share leading-edge technologies. It’s going to be a hive of all sorts of activities—a magnet for all attendees.

Here’s a rundown of what you’ll experience in Austin, June 18-22.

  • In the second year of the popular World of IoT, we’ve added new interactive experiences for attendees to enjoy, building on last year’s successes. We have a tech puzzle for avid problem solvers, a new virtual reality experience and our very popular tear-downs . These activities are part of the popular DAC Attack game, available in the DAC mobile app. We give out prizes—Samsung VR headset, Bose noise canceling headphones, Amazon gift cards, and more— to the highest points winners on Wednesday at 5:00 p.m. from the DAC Pavilion. And don’t forget the return of the Makers Market and the IP Pavilion, all within the World of IoT. It’s almost like an entire event in and of itself!

Read the rest of #54DAC 9: Live from Austin: The DAC Exhibition floor; 3 Full-days of Activities

#54DAC #8: Awesome keynotes show how our community has grown

 
May 12th, 2017 by Michael (Mac) McNamara, Gen Chair 54th DAC; Pres & CEO Adapt-IP

In case you missed it, we’ve announced our 2017 keynoters, a group that (including the luminaries giving SKY talks) gives you six more very good reasons to be in Austin the fourth week in June. All the information you need on the lineup is here. I know you are perhaps too busy to dig through this, so LMGTFY and share with you some highlights:

#54DAC 7: IoT: Tales from the Frontline.

 
April 21st, 2017 by Michael (Mac) McNamara, Gen Chair 54th DAC; Pres & CEO Adapt-IP

We hear from media outlets that Internet of Things (IoT) solutions will be soon be surrounding us in our homes, our offices, our schools; in factories and farms; working to make our life better, or perhaps working to eliminate our species!  Well, 50+ years has taught us that any new technology happens first at DAC, and adding credence to the media’s predictions, you will see IoT technology information and insights everywhere the 54th Design Automation Conference.

There is not some new job title of “IoT engineer.” Instead our familiar, experienced analog, mixed-signal engineers, RF engineers, server architects and mobile developers and verification teams are applying our tools and their skills in this new application area. Since IoT design elements touch most EDA engineering disciplines, we’ve made it easier for DAC attendees to learn what they need to know about IoT trends and technology wherever they are at the Austin Convention Center.

Here’s a sampling of IoT-related presentations that can be found in keynotes, SKY Talks, fireside chats, DAC Pavilion sessions and tutorials:

Read the rest of #54DAC 7: IoT: Tales from the Frontline.

#54 DAC 6: Program Finalized; Advanced Registration Now Open!

 
April 10th, 2017 by Michael (Mac) McNamara, Gen Chair 54th DAC; Pres & CEO Adapt-IP

A DAC winter meeting held in sunny Mexico isn’t what it’s cracked up to be. (Although we did enjoy the break from this winter storms!)

Everybody thinks the Executive Committee members are lounging on the beach enjoying drinks with little umbrellas in them. That couldn’t be further from the truth!

In fact I and 15 other EC members spent most of our February meetings in Puerto Vallarta in a windowless hotel conference room, refining the DAC program and finalizing the details of the big event in Austin, June 18-22.

The hard work of the technical program chairs comes together in rooms just like that one, during the winter of each year, as we knit together the fruits of months of labor by our sub committees to form a coherent program on the projection screen. This year’s program is benefitting big time from that hard work: It’s one of the most compelling I’ve seen in my 20+ years of either attending or being a part of DAC.

Each year it just gets better. Consider that this year the Designer Track has grown to 18 sessions, almost doubling in size in two years. This includes eight invited sessions, two panels, eight submitted sessions and more than 80 poster sessions. We had a record number of submissions for this year—149.

What else is in store for attendees? Plenty.

We put together 44 technical sessions, more than 130 research papers, 6 panels and 11 invited sessions spread throughout our seven main topic areas—Automotive, Design, EDA, Embedded Systems & Software, IoT, IP and Security. We.ve identified 16 sub-topic areas—from general business to circuit design to low power and reliability to test and verification—to help attendees better tune their experience based on their interests. Some broader areas, for example IoT, have papers spread throughout the program, whether it might be a poster session, an invited presentation, a keynote or a SKY Talk.

This valuable content—created by engineers for engineers—will be found throughout the Austin Convention Center. We’ll have content on the exhibit floor in the DAC Pavilion, in the hallways, meeting rooms on all floors; in short, all over the location.

Take a tour of the program here and start to tick off what you’re not going to want to miss. Me? I want to see the Monday afternoon panel Growing IC Design and Ecosystem in China, moderated by EE Times editor Junko Yoshida; Joe Costello’s Monday morning keynote, IoT: Tales from the Front Line; Tuesday afternoon’s RISC-V Implementation Considerations presentation; the Sunday DAC workshop on autonomous vehicles. I could go on, but you have your own interests, so check it out.

It’s easy to register too, and I hope to see you there. Maybe then we can have an umbrella-festooned cocktail or two!

Register for DAC at:  https://dac.com/content/registration

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