Bridging the Frontier
Bob Smith, Executive Director
Bob Smith is Executive Director of the ESD Alliance responsible for its management and operations. Previously, Bob was senior vice president of Marketing and Business Development at Uniquify, responsible for brand development, positioning, strategy and business development activities. Bob began his … More »
June 8th, 2017 by Bob Smith, Executive Director
The following week, we’re off with rest of the semiconductor design ecosystem to Austin, Texas, for the Design Automation Conference (DAC). Events kick-off Sunday, June 18, and go through Thursday, June 22, with exhibits running Monday through Wednesday from10 a.m. until 6 p.m. at the Austin Convention Center.
The opening event, “Electronic Design Automation (EDA) in the Age of the System,” will update attendees on the state of EDA. Chief Analyst Laurie Balch of Gary Smith EDA will present the firm’s findings at this ESD Alliance-hosted event Sunday from 5 p.m. until 5:30 p.m. in Ballroom D of the convention center. A DAC reception immediately follows on the Fourth Floor Foyer.
We’re pleased that so many of our board members will have visible roles in the DAC program, starting with Amit Gupta, president and CEO from Solido, who will moderate a panel titled, “EDA Powered by Machine Learning,” It will be held Monday in Room 10AB from 10:30 a.m. until 11:30 a.m
A “One-On-One” discussion with Lip-Bu Tan, president and CEO of Cadence, and Ed Sperling, editor-in-chief of Semiconductor Engineering, will be held Monday from 11:30 a.m. until 12:15 p.m. at the DAC Pavilion. Lip-Bu will share insights about big changes in the data center and end markets, the rise of machine learning, growing challenges in system design, and what to watch for in China.
May 25th, 2017 by Bob Smith, Executive Director
The ESD Alliance has a new look with a refreshed website, thanks to our tenacious Member of the Technical Staff Paul Cohen who oversaw the entire project.
And, what a project it was! The design streamlines our activities, all found in neatly packaged pull-down sections running across the top right of the home page. You’ll find information about us, including the staff, board of directors, committees and member companies. Our active initiatives provide the forum for member companies to address issues of common concern and fall broadly into five categories –– risk management, growth and efficiency, industry voice, events and education, and market information. All are outlined in detail and we invite participation from member companies. Naturally, we have a section on news and events that hosts our newsletters and my blog. More content is being added regularly. Please let Paul (email@example.com) or me (firstname.lastname@example.org) know what you think.
Of course, the next event is the Design Automation Conference (DAC), the premier conference for design and automation of electronic systems, long sponsored by the ESD Alliance. DAC is being held this year at the Austin Convention Center in Austin, Texas.We’ll be in booth #2123 Monday-Wednesday, June 19-21, from 10 a.m. until 6 p.m.
Please stop by our booth to see us. We’ll have our latest newsletter and other handouts. And, make sure you visit our member companies’ DAC booths as well. By all means, tell them I sent you!
May 9th, 2017 by Bob Smith, Executive Director
One of the most popular and enduring programs the ESD Alliance offers its members is the quarterly Market Statistics Service (MSS) report containing detailed revenue data for the EDA, Semiconductor IP and design services industries. The report compiles data submitted confidentially by public and private EDA and semiconductor IP companies into tables and charts listing the data by product category and geographic region.
Read the rest of Twenty Years of the ESD Alliance’s Market Statistics Service
April 25th, 2017 by Bob Smith, Executive Director
CAST of Woodcliff Lake, N.J., has 23 years of SIP experience and offers a range of production-proven SIP cores that include controllers and processors, compression, peripherals, interconnect and security, and encryption.
SoC Solutions from Suwanee, Ga., enables next-generation IoT and Machine to Machine (M2M) silicon devices by supplying processor-based IP and services to build innovative, low-power “connected” products.
According to Jim Bruister, SoC Solutions’ CEO: “The ESD Alliance is the all-important connection to the semiconductor design ecosystem. For a company like ours, there’s no better organization to belong to for both the networking opportunities and the Semiconductor IP Working Group that’s helping to define so many critical aspects of our market segment.”
April 20th, 2017 by Bob Smith, Executive Director
The semiconductor design ecosystem came out in force Thursday, April 6, for the CEO Outlook at Synopsys in Mountain View, Calif. It was a great crowd and an exceptional panel moderated by Semiconductor Engineering’s Ed Sperling. Thanks to Lip-Bu Tan of Cadence, Wally Rhines from Mentor, ARM’s Simon Segars and Aart de Geus at Synopsys for their insights and a lively discussion.
Our special guests that night were from the Dwight D. Eisenhower School for National Security and Resource Strategy, part of the National Defense University (NDU). The ESD Alliance hosts a yearly visit from the NDU students and organizes meetings with noted semiconductor companies in Silicon Valley to help educate them about our industry and its importance to the global electronics industry.
A picture is worth a thousand words, so I’ll dispense with a long blog and let the photos tell the story.
If you’re craving words to describe the evening, Peggy Aycinena wrote a blog filled with color and loads of details on EDACafe. It can be found at: http://bit.ly/2kjVajD
Read the rest of A Picture is Worth a Thousand Words –– Photos from the CEO Outlook!
March 28th, 2017 by Bob Smith, Executive Director
The spectacular news this week from the ESD Alliance’s Market Statistics Service (MSS) that revenue increased 18.9 percent for Q4 2016 will be an exclamation point to next week’s CEO Outlook.
For example, revenue for Q4 in all four geographic regions –– Americas, Europe, Middle East and Africa, and Japan and Asia/Pacific –– increased 18.9 percent for Q4 2016 to $2455 million, compared to $2064.5 million in Q4 2015. All product categories saw fourth-quarter growth. In fact, CAE, Semiconductor IP, IC Physical Design & Verification and PCB/MCM reported double-digit increases. Another positive sign is employment is up 6.6% overall.
CEO Outlook attendees can expect to hear much more about industry opportunities for growth and challenges as Ed Sperling, editor-in-chief of Semiconductor Engineering, moderates the panel of four of our most visible CEOs and Alliance Board Members. They are: Aart de Geus, CEO at Synopsys, Lip-Bu Tan, president and CEO of Cadence, ARM’s CEO Simon Segars and Wally Rhines, chairman and CEO of Mentor Graphics and board sponsor for the MSS.
March 17th, 2017 by Bob Smith, Executive Director
Please Note: With regrets, we are postponing the “Energy Policy and Strategy for the IoT Era,” the panel on the new energy rules for PCs from the California Energy Commission Thursday, March 23, due to unforeseen circumstances. Stay tuned for updates.
After listening to our members who told us they missed the yearly CEO forecast, it’s a pleasure to let you know the ESD Alliance is bringing back an evening with the leaders of our industry. The 2017 CEO Outlook will be held Thursday, April 6, from 6:30pm until 8:45pm at Synopsys in Mountain View, Calif. A private reception for ESD Alliance members only to mingle with speakers will begin at 5:30pm.
Four of our industry’s most visible CEOs will discuss their views on the future of the system design ecosystem in what promises to be a wide-ranging and enlightening panel discussion. The four panelists for the evening are: Aart de Geus from Synopsys, Lip-Bu Tan of Cadence, ARM’s Simon Segars and Wally Rhines of Mentor Graphics. Each will share his views on where the semiconductor industry and system design ecosystem are heading, review trends and point out potential opportunities and danger signs ahead. After brief opening statements about the future of the industry, an interactive audience discussion will follow.
March 7th, 2017 by Bob Smith, Executive Director
Fresh from our “Ride with the Verify Seven” evening co-hosted with ESD Alliance member company OneSpin during DVCon, we’re planning our next event with another member company –– Sonics –– Thursday, March 23.
The panel, “Energy Policy and Strategy for the IoT Era,” moderated by Grant Pierce, Sonics’ CEO and chairman of the Alliance board of directors, will outline new energy rules for PCs set by the California Energy Commission (CEC). A panel discussion will look at how these new rules affect the system design ecosystem and how the industry will adapt to them.
The standards, primed to begin January 1, 2018 and roll out through July 2021, cover desktop computers, notebooks and laptops, small-scale servers, workstations and monitors, the top consumers of electricity in California. Estimates are staggering –– the state reports consumption of about 5,610 gigawatt hours of electricity or 3% of residential electricity use and 7% commercial. The CEC determined something needed to change, even though many manufacturers build seemingly energy-efficient products. The new standards are estimated to save 2,332 gigawatt hours per year and reduce utility bills by more than $370 million, enough energy to power about 350,000 California homes a year while reducing greenhouse gas emissions.
February 24th, 2017 by Bob Smith, Executive Director
The Super Bowl wasn’t the only festive event over the last few weeks! The Electronic Systems Design ecosystem honored Andrzej Strojwas as the 2016 Phil Kaufman Award recipient during an awards ceremony and dinner attended by close to 200 of us from the industry. It was held Thursday, January 26, at the Fourth Street Summit Center in San Jose, Calif.
For those of you who don’t know Dr. Strojwas, he is PDF Solutions’ chief technologist as well as the Keithley professor of Electrical and Computer Engineering at Carnegie Mellon University. He was recognized with the award for his pioneering research in the area of DFM in the semiconductor industry.
The Kaufman Award is presented annually by the ESD Alliance and the IEEE Council on Electronic Design Automation (CEDA). For more information, check out: http://bit.ly/2l95wTO
As I did with the RISC-V event, I won’t try to recapture the evening when two of our favorite chroniclers Peggy Aycinena and Paul McLellan covered the evening so masterfully and neatly depicted the mood. (See the links to their blog posts below.) Instead, I’ll offer you a look at who was there through photos taken by the Alliance’s Paul Cohen and Julie Rogers and ace photographer Ross Mehan of Ross Mehan Photography. The video, produced by Andrew Mellows Video, will be available on the ESD Alliance website shortly.
February 23rd, 2017 by Bob Smith, Executive Director
I promised in my last post a special blog post with great photos highlighting the Phil Kaufman Award Ceremony and Dinner January 26. It will go up Monday.
But first, the news that the ESD Alliance will exhibit at DVCon at the DoubleTree Hotel in San Jose, Calif. We’ll be in Booth #100 in the foyer, so please stop by if you’re attending.
During DVCon, we’re co-hosting with OneSpin Solutions a panel, “Ride with the Verify Seven,” moderated by Jim Hogan of Vista Ventures featuring six verification leaders who grew their companies from startup to medium-sized industry player. It will be held Monday beginning at 7 p.m., after the Booth Crawl, until 8:30 p.m. Light refreshments and drinks will be served.
The event is open free of charge to all Alliance member companies and DVCon attendees. Non-members of the Alliance or anyone without a DVCon badge are invited to attend for a fee of $40. Registration information and more details on the event can be found at: http://bit.ly/2kNWx6T