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Posts Tagged ‘IC’

Hurricane FinFET (Part 2)

Wednesday, March 9th, 2016

So, FinFETs rule! They give the designer so much flexibility in trading off power and performance that it should be a no-brainer to adopt the technology–right?

Well, every silver lining has to have a cloud, and in the case of FinFETs there are quite a few.

I polled a number of layout designers who have first-hand experience of laying out FinFET designs and asked them “What’s the impact of FinFET?”. Here’s what they told me requires them to do extra work:

  • First off is the sheer number of rules that they have to be conscious of. The number of rules has more than doubled compared to a 40-nm process. Of special concern are some of the density rules that now have to be applied to a lot more layers.
  • Another area you have to pay particular attention to is maximum diffusion space. This forces devices to have guardrings around them so that you do not have too large a diffusion space. The diffusion in the guardring essentially breaks the space check. So you either have to have devices very close together or spaced by guardrings.
  • Process restrictions require that every fin has to have an equal height. In addition there are strict limitations on the sizes of “W” and “L” that can be used. As a result a device that requires a large “W” (width) has to be quantized into multiple fin units that utilize the acceptable “W” and “L”.
    What this means in practice is that an innocent-looking single device in the schematic can be 100 devices in the physical layout! Add to that the fact that fins have to snap to specific grids and you have a massive layout challenge for even a simple circuit.


We’ve Come a Long Way! (Part 3)

Monday, February 15th, 2016

I left off in part 2 of this blog asking the question: “Have we exhausted all avenues in our search for layout productivity?”

Although there has been no revolutionary technology as with the initial CALMA systems, there have been some incremental improvements that help oil the gears when doing layout.

On-line DRC has been one such improvement. Having the ability to check the layout for design rule violations incrementally, as you complete more and more of the design, made it easier to implement changes. Violations were displayed in the layout, making it easy to find and fix them. However, checking the layout connectivity versus the schematic was still a batch task that could only be run when the design was fully implemented. The connectivity of the physical layout had to be extracted in order to compare against the logical connectivity.

As EDA marched on, with each new crop of more powerful workstations came the next generation of interactive tools. If you could compute the design rule checks fast enough, why not show them dynamically as layout geometries were being created? And so Design-Rule-Driven (DRD) layout was born.

We’ve Come a Long Way! (Part 2)

Wednesday, February 10th, 2016

If I say ‘sticks’ to you, what comes to mind? Well, you could reply with “bits of wood” or “an American rock band from the 70’s” or “a river in Hades” and you would be correct. However, when you ask the question in the context of EDA, well, that’s a different story.

‘STICKS’ or ‘stick diagrams’ refers to a technology called symbolic layout. My first introduction to symbolic layout was the CALMA STICKS package that emerged around 1983.

STICKS was a netlist-driven symbolic design package that produced correct-by-construction physical layout directly from the logical netlist. Although a great concept, it never really took off. The effort to bring the logical connectivity into the layout by means of a netlist did not deliver a high-enough ROI in the eyes of the layout community.

We’ve Come a Long Way! (Part 1)

Thursday, February 4th, 2016

It’s amazing what you find when you clean out your garage. I came across some old photographs of the first CALMA systems I worked on. Boy, have we come a long way since those days!

Those early CALMA Graphic Data Station (GDS) systems that I worked on back in the late 1970s were considered revolutionary. Why revolutionary? Well before they came along, making the masks for an IC was a real pain. Here’s a brief recap of what you had to do to:

Before GDS, the IC layout engineer would have to draw the circuits on large sheets of grid paper, using a different color for each layer of the circuit. Then they would produce a mask of each layer by cutting the shapes into a peel coat material such as Rubylith. To get a rectangle for example you would cut the four edges that made up the rectangle through the top layer of the Rubylith but not through the base layer. The peel coat material would be removed, leaving the rectangle exposed. The sheets were then photographically reduced to the real size of the IC. A stepper was then used to produce the physical masks by replicating the sheets as many times as would fit on a mask that was the real size of the wafer. Typical wafer sizes back then were around 4 inches. As you can imagine, this was very time consuming and very error-prone.


S2C: FPGA Base prototyping- Download white paper

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