Posts Tagged ‘FinFET’
Monday, May 23rd, 2016
I just wanted to take a moment to personally invite you to attend Synopsys’ Custom Compiler lunch event at DAC 2016 on Tuesday, June 7 in Austin, TX. At this event, engineers from GSI Technology, Samsung, STMicroelectronics, and Synopsys’ IP Group will showcase their experiences using the new Custom Compiler custom IC design tool with Visually-assisted Automation technologies.
As you’ll recall, Synopsys unveiled Custom Compiler on March 30 of this year at SNUG Silicon Valley. Custom Compiler is a new custom IC design solution that closes the FinFET productivity gap by cutting custom layout tasks from days to hours. It offers a fresh approach to custom design that employs Visually-assisted Automation technologies to speed up common design tasks, reduce iterations and enable reuse. Visually-assisted Automation technologies are a unique set of productivity aids that leverage the graphical use model familiar to layout designers while eliminating the need to write complicated code and constraints.
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Tags: Custom Compiler, custom IC design, DAC 2016, FinFET, layout, SNUG, Synopsys, visually-assisted automation
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Tuesday, May 17th, 2016
In the last blog I outlined the kind of tool that layout engineers need in order to get a good placement that delivers robust working silicon within the confines of the FinFET process. We concluded that a guided/interactive approach that is fast and easy to refine such that you do get the result you want is the way to go.
So where else can we look for more efficiency during layout? Well, once you have placed your devices, the next step is to route up all the connections that cannot be completed by simple abutment. Again, because you could be dealing with hundreds of devices [remember the differential pair example? See the “Current Solutions for FinFET (Part 1)” blog] the routing task is one that absolutely screams out for an automatic approach, and there have been lots of efforts at automating custom routing in the past.
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Tags: automation, constraints, custom layout, efficiency, FinFET, routing, user guidance
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Tuesday, May 10th, 2016
Over the last series of blogs we have looked at which tools the layout engineer has available to him/her to help deal with the complexity of doing layout with FinFETs. Even though there are tools that help, the fact is there is still a productivity hit when comparing the time it takes to do a FinFET-based layout vs. a planar CMOS layout. When I asked my layout colleagues “How much longer does it take to do a FinFET-based design vs. planar CMOS?”, they said it takes 2-3X longer.
So, if we are to recoup layout productivity when doing a FinFET-based design, which areas should we focus on? Well, let’s start at the very beginning, which, according to Julie Andrews in The Sound of Music, is a very good place to start. The task of generating the devices and placing them such that they meet all the design rules and will produce a robust working design is about 30% of the layout time. So if we can speed up this task then we will gain back some of the productivity we lost due to the complexity of the FinFET process.
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Tags: analog, custom design, FinFET, layout, planar CMOS
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Friday, April 29th, 2016
What is electromigration (EM) and why is it something we should care about?
Here’s the definition of electromigration from Wikipedia: “Electromigration is the transport of material caused by the gradual movement of the ions in a conductor due to the momentum transfer between conducting electrons and diffusing metal atoms.”
Put simply, when the current density gets too high for a given wire width, you get problems. These problems manifest themselves in two ways, either a void in the metal wire that creates an open circuit or a hillock that creates a short to another wire. Either way your chip fails. Electromigration is made worse by temperature and mechanical stresses.
Electromigration in the FinFET process is now a first-order effect and has a huge impact on the Mean Time To Failure (MTTF) of a metal wire. So, as you can imagine, to ensure you have a robust design that will last, great care has to be taken when choosing wire widths for interconnect and power grids.
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Tags: custom design, CustomSim, electrommigration, EM, FastSPICE, FinFET
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Wednesday, April 6th, 2016
So, hopefully, you are now aware of Synopsys’ new Custom Compiler solution tuned for rapid implementation of FinFET custom designs. Custom Compiler features a pioneering visually-assisted automation flow that speeds up custom design tasks from days to hours, reduces iterations and enables reuse–very exciting stuff!
But I want to continue my previous discussion thread to help you get a better understanding of the scope of the challenges inherent in FinFET design (and hopefully avoid some pitfalls).
So, going back to where I left off earlier… PCells for custom layout have been a ‘no brainer’ for decades. They have done all the heavy lifting with respect to generating correct-by-construction layout and have been the most important ‘power’ tool for custom layout engineers. Now however, given the complexity of the FinFET process, they become absolutely vital.
Generating a FinFET device is easy when you have a PCell. When coded correctly, it will automatically generate the device such that the fins are properly spaced on the requisite ‘fin grid’ and that all the rules for Poly width/length, Diffusion width/length, Poly cuts and the like are adhered to. In addition to constructing the device design rule correctly, the PCell will also ensure that the metals in the device are colored correctly and abide by the color-related rules. As you can imagine, there is a lot of stuff going on in a FinFET PCell, but there is more. FinFET PCells have to be ‘smarter than the average PCell’ and they have to be in tune with the layout methodology.
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Tags: correct-by-construction, Custom Compiler, custom layout, DRC, FinFET, iPDK, PCell, routability
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Wednesday, March 30th, 2016
Over the last few blogs I have outlined some of the productivity challenges that the FinFET process brings with respect to custom layout. Today Synopsys unveiled Custom Compiler and ushered in a new era of visually-assisted automation. Custom Compiler has all the good stuff I’ve been saying is needed in earlier posts: a new custom design solution that closes the FinFET productivity gap by shortening custom design tasks from days to hours.
This is not a revamp of the old constraint-based legacy approach, it’s a fresh approach to custom design that employs visually-assisted automation technologies to speed up common design tasks, reduce iterations and enable reuse.
What’s visually-assisted automation, you may ask?
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Tags: constraints, Custom Compiler, custom design, DRC, electromigration, EM/IR, FinFET, layout, SNUG, StarRC, Synopsys, visually-assisted automation
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Monday, March 28th, 2016
What tools do we have in our FinFET toolbox that can help layout engineers manage the complexity that FinFETs inherently bring?
Well for my money, the best and most powerful tool we have to tackle FinFET complexity is the good old parameterized cell or PCell. PCells are not new, they have been around since the CALMA GDS days and along with Schematic-Driven Layout, have been instrumental in boosting layout productivity, as I have mentioned in my previous posts. PCells have typically been used to generate physical layout of pretty much all the devices needed for custom layout, from resistors to inductors, capacitors and, of course, the transistor. That is still the case for FinFET designs; however the role of the PCell has now been expanded to include the schematic PCell.
So what’s the big deal about a schematic PCell, you might ask? And why didn’t we have them before?
Well, some companies did use schematic PCells, but mainly to generate symbols. With FinFET there are many more reasons that a schematic PCell should be used. It boils down to three things: complexity, aesthetics, and productivity.
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Tags: custom design, FinFET, PCell, Schematic PCell, Synopsys
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Friday, March 18th, 2016
Continuing on the theme of FinFET layout, let’s consider what you have to do for routing. Again drawing on the experience of my layout colleagues who are still ‘in the business’ and dealing with FinFETs, here are a few landmines you will have to deal with.
One particular issue they encounter is that although the base layers have shrunk considerably, the shrink of the routing layers has not kept pace. Each new node has brought us smaller transistors, but the minimum metal pitch has not really changed. This really impacts layout floorplanning because designs that were once dictated by device area are now dictated by the ability to route the required signals. Double-/triple-patterning compounds the issue even further.
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Tags: electromigration, EM, FinFET, floorplanning, IR, layout, planar, routing, Synopsys, topology
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Wednesday, March 9th, 2016
So, FinFETs rule! They give the designer so much flexibility in trading off power and performance that it should be a no-brainer to adopt the technology–right?
Well, every silver lining has to have a cloud, and in the case of FinFETs there are quite a few.
I polled a number of layout designers who have first-hand experience of laying out FinFET designs and asked them “What’s the impact of FinFET?”. Here’s what they told me requires them to do extra work:
- First off is the sheer number of rules that they have to be conscious of. The number of rules has more than doubled compared to a 40-nm process. Of special concern are some of the density rules that now have to be applied to a lot more layers.
- Another area you have to pay particular attention to is maximum diffusion space. This forces devices to have guardrings around them so that you do not have too large a diffusion space. The diffusion in the guardring essentially breaks the space check. So you either have to have devices very close together or spaced by guardrings.
- Process restrictions require that every fin has to have an equal height. In addition there are strict limitations on the sizes of “W” and “L” that can be used. As a result a device that requires a large “W” (width) has to be quantized into multiple fin units that utilize the acceptable “W” and “L”.
What this means in practice is that an innocent-looking single device in the schematic can be 100 devices in the physical layout! Add to that the fact that fins have to snap to specific grids and you have a massive layout challenge for even a simple circuit.
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Tags: analog, custom design, design rules, double-patterning, FinFET, IC, layout, schematic, SoC
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Wednesday, February 24th, 2016
In my last post, I said: “A hurricane has made landfall and its name is FinFET”. OK, it’s a little corny, but it was not meant to convey a sense of impending doom for custom layout productivity. No question that hurricanes are disruptive, but humans can adapt to even the worst nature can bring. And FinFETs bring tremendous benefits along with the disruption.FinFETs are without doubt the most radical shift in semiconductor technology in decades, but moving to FinFETs is absolutely necessary. As feature sizes became finer, high leakage current due to short-channel effects threatened to put the brakes on scaling. FinFETs address the leakage issue and give Moore’s Law a new lease of life.Today the bulk of design starts are at the established nodes above 28 nm, so not everyone doing custom layout has experience with FinFETs. For those who have not yet felt the ‘winds of change’ that FinFETs bring, here is a brief primer.
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Tags: 3D, custom design, EDA, FinFET, layout, Moore's Law, MOSFET, planar, SoC, Synopsys, UC Berkeley
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