When it comes to stimulating, it doesn’t get better than stepping out of a session at IEDM in San Francisco to take a conference call from Glasgow. On Tuesday, December 11th, I stepped out of Session 9 and a presentation on spintronics to speak with Dr. Asen Asenov about a different device technology.
Asenov is a 20-year veteran of the University of Glasgow, where he serves as James Watt Professor of Electrical Engineering and heads up the Glasgow Device Modeling Group. He is also founder of Glasgow-based Gold Standard Simulations (GSS), a company that specializes in simulating statistical variability in nano-CMOS devices.
We spoke on December 11th because GSS announced that day the results of research “comparing the differentiation between metal gate first and metal gate last FDSOI [fully-depleted silicon-on-insulation] approaches, and comparing it to equivalent bulk MOSFETs.” Based on that work, the company announced that gate-last technology “offers significant advantages” over gate-first technology for devices built on 32- or 28-nanometer FDSOI, and noted that both nodes “significantly outpace equivalent bulk MOSFETS with respect to low-power SRAM design.”
