Posts Tagged ‘Synopsys’
Sunday, June 7th, 2015
Omygosh, DAC’s here again! Has it already been a year? Apparently yes, and apparently once again the Design Automation Conference is going to be great. And how does one know? Because once again the DAC Executive Committee is great, lead in 2015 by the more-than-capable Anne Cirkel (Mentor’s own). Everything from academia to industry, from networking to hard-core learning (read, ‘Nerd Alert!)’, from food and libation to product announcements: DAC is always special.
So today is Sunday, which in the world of DAC is a lovely day full of workshops for those interested in the newest, and social opportunities for those interested in the noshing and nattering. Sunday is also lovely, because it’s a moment for astonishing realizations, and this year’s 52nd DAC Sunday is no different. Here are my 10 favs:
10 — Per Stanford’s Philip Wong speaking in Workshop 2, carbon nanotubes are smooth which helps with mobility-restricting surface roughness and band-gap issues. Also CNTs are no longer “a bowl of spaghetti” when manufactured. Now they’re 99% orderly and courteously aligned. (read, ‘Is asking about the other 1% a legitimate question?’)
9 — EDA’s own Karen Bartleson of SNPS fame, has not only just completed 2 years of distinguished service as President of IEEE’s worldwide Standards Organization, she’s now been nominated to serve as President of the Whole Enchilada; Bartleson’s running for President of the IEEE itself. In a word, Wow!
8 — Design Automation Summer School, for those who have not been keeping up (read, ‘me’), is no longer a week-long confab in July. These days Summer School is a one-day event on DAC Sunday. Still highly attended and full of pithy content for The Young & The Restless in EDA.
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Tags: Ajoy Bose, Alain Labat, Anne Cirkel, Ansys, Apple, Atrenta, Cadence, DA Summer School, DAC, Design Automation Conference, EDAC, edaForum, Elliot Garbus, Fiat Chrysler Automotive, Four Seasons, Harvest Management Partners, IEEE, Intel, Karen Bartleson, Klauss Busse, Mentor Automotive, Mentor Graphics, Patrick Groenveld, Philip Wong, Soha Hassoun, Synopsys, Wally Rhines, WWDC15
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Tuesday, April 7th, 2015
Frank Schirrmeister, Group Director of Product Marketing for the System and Software Realization Group at Cadence, had just returned from DATE in Grenoble when we spoke several weeks ago about the philosophy and technology behind Cadence’s emulation business unit. First, however, we spoke about Grenoble.
I asked Frank if DATE had been a success this year and he said, “Absolutely, yes. It was very interesting as it has transformed from a generic show into more of a technical conference. So the focus now is on the sessions.
“Particularly interesting for me, I was chair for a session about tools for the IoT. Jan Rabaay from U.C. Berkeley, always a good speaker, gave a great presentation on wearable trends. NXP also participated, talking about the connected car, and ARM spoke about their embed OS for the edge nodes. Also among those topics, we talked about debug. It was all very good.”
Having enjoyed DATE many times myself, I asked Frank what he thought distinguished the conference from DAC. He said, “First of all, DATE was in Grenoble, which is always a great destination. Then, of course, at DATE you see the European point for view.
“For instance, I had a presentation for my session regarding automotive issues, and included material of interest to our customers in Japan and Europe. The share of semiconductors in cars from those markets focuses more on the mission-critical pieces in the design. The focus is different for automotive customers in North America, where it centers more on mobile connectivity within the vehicle.”
All of this being very interesting, I turned the conversation to the real reason for our phone call: To allow Frank to clarify emulation at Cadence.
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Tags: Cadence, DATE, FPGA-based prototyping, Frank Schirrmeister, Mentor Graphics, Palladium, Protium, Synopsys
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Monday, March 23rd, 2015
The last time I spoke at length with OneSpin’s Dave Kelf, the conversation was all about the Cloud. This week we picked up where we left off, talking about the Cloud, but then moved on to the Wild West. Dave is quite taken with the idea that the current situation in EDA is on par with the Wild West, that mythical place where a lack of structure and entrenched establishment allows true innovators to run wild free. First however, we caught up with OneSpin and the Cloud.
Dave said, “These days, engineers cannot afford to stick their necks out. Neither their managers nor their corporate leadership want to take risks, and the engineers know it. Although engineers realize moving design to the Cloud makes sense, when they try to explain that to their bosses or corporate lawyers it often leads to legal discussions around the problems of having [propriety] IP leave the company’s server.
“At OneSpin, however, we are able to eliminate these issues by generating abstract verification proof problems that go to the Cloud for computation without the transfer of IP or even [identifiable markers], assuring our customers that the process is very secure. Moving to the Cloud means design teams will have access to infinite computing, with huge verification jobs running simultaneously.”
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Tags: Amazon, Assertion-Based Formal Verification, Broadcom, Cadence, Dave Kelf, Fujitsu, GlobalFoundries, Google, high-level synthesis, Intel, Microsoft, NXP, OneSpin, OneSpin 360 DV-Inspect, OneSpin 360 DV-Verify, Qualcomm, Raik Brinkmann, Samsung, Silicon Cloud, Sony, Synopsys, SystemC, TSMC
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Thursday, March 5th, 2015
What if I were to tell you that I attended a conference where people were really excited to be there, where the exhibit hall was filled with a crush of people making their way from booth to booth, talking with exhibitors and exchanging business cards madly. A conference where the South of the exhibit hall was dominated by Synopsys, the East by Cadence, and the West by Mentor, and where at the happiest hour, libations and snacks flowed freely in a sub-set of the booths and the whole exhibit hall became even more animated.
What if I told you the technical portion of the conference included a variety of content — touching at times on autos, wearables, the IoT, IP, standards, and verification — excellent panel discussions, well-attended poster sessions, detailed tutorials, and a keynote from the CEO of the largest company in the industry delivered to a packed, SRO ballroom full of designers, engineers, and engineering managers.
Finally, what if I told you the highly capable staff of MP Associates was running the whole thing with their usual aplomb, attending to details as diverse as registration, sound systems, lunch tickets, speaker logistics, and awards presentations.
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Tags: Cadence, DAC, Design Automation Conference, DVCon, DVCon Europe, DVCon India, DVCon Silicon Valley, Mentor Graphics, MP Associates, Synopsys
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Monday, February 16th, 2015
Lauro Rizzatti, formerly VP of Marketing at verification-centric EVE, thought he was going to move to Oregon last year and retire, but he was wrong. Instead he is busier than ever, hard at work both in the EDA tech sector and in the larger world of venture capital.
Lauro is consulting with Mentor Graphics to promote the company’s ever-expanding presence in the world of emulation, and he is also involved with the Oregon Angel Fund, a group of investors led by Eric Rosenfeld and former SpringSoft USA President Scott Sandler, also busy residents of Oregon.
Mentor is one of the top two emulation companies in the world, along with Cadence. Synopsys also has a foot in the door of that market thanks to their 2012 acquisition of EVE, which brings us back to Lauro. It was after his year spent at Synopsys following the acquisition that he ‘retired’ to Oregon. Clearly, however, it was a waste of his 30+ years of experience in verification to not have him continue contributing to the conversation around that technology, hence his consulting work at Mentor.
I had a chance to talk with Lauro about all of this in a recent phone call, a discussion in which he celebrated the green of Oregon while also gently chiding the endless rain that makes that lushness possible.
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Tags: Cadence, custom FPGAs, Emulation, Eric Rosenfeld, EVE, IBM, Lauro Rizzatti, Mentor Graphics, Oregon Angel Fund, Scott Sandler, SPICE, Synopsys, Xilinx
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Thursday, November 13th, 2014
Dreary sentiments notwithstanding from several panelists at an ICCAD evening session on November 2nd in San Jose, SRC’s Dr. Bill Joyner espoused optimism and energy for the future of EDA, even if said future doesn’t include the venerated Moore’s Law stretching off into infinity forever.
As moderator, Joyner convened the panel, “Moore’s Law is dying, EDA to the rescue!”, and turned over the podium straightaway to University of Pittsburgh’s Dr. Alex Jones for the first 20 minutes, which allowed the professor to report out on a 3-year Computing Community Consortium effort, just completed, to examine and exhume EDA from the doldrums.
The CCC’s group of 50+ academic and industry leaders have been meeting since 2012 at a series of SIGDA/CCC-funded workshops hoping to impact the future by nudging industry and academia into more productive avenues of research and development in design automation.
The report the committee published, “Workshops on Extreme Scale Design Automation (ESDA) Challenges and Opportunities for 2025 and Beyond”, was available in paper form at the back of the room during the ICCAD panel and has subsequently proved to be great reading, and fodder for a future blog. But this blog is a thumbnail sketch of the November 2nd discussion, so please read on.
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Tags: ACM Sigda, Computing Community Consortium, Dr. Alex Jones, Dr. Jacob White, Dr. Leon Stok, Dr. Luigi Capodieci, Dr. Patrick Groeneveld, Dr. Todd Austin, Dr. William Joyner, EDaaS, GlobalFoundries, IBM, ICCAD, MIT, SRC, Synopsys, University of Michigan, University of Pittsburgh
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Thursday, September 25th, 2014
Last week I had a chance to chat by phone with Accellera Chair Shishpal Rawat, and when I say chance that’s accurate. Rawat is so busy these days, it’s hard to believe he has time for any extraneous conversations. Not only does he have a full-time job at Intel, he has been chair of Accellera for four years and now is ramping up to take over the reins at CEDA at well.
Among other activities, both Accellera and CEDA sponsor several key conferences in the industry. Accellera is the primary sponsor of the Design and Verification Conference and Exhibition (DVCon). I asked Shishpal about this year’s efforts to take DVCon on the road and how that dovetails with the changes he’s seen at Accellera over his years of leadership.
He said, “Without a doubt, the biggest change is the international outreach that we are now doing in our programs. DVCon will debut in Bangalore this month and will debut in Europe next month on October 14th and 15th in Munich. Expanding the conference this way has required a great deal of work on the part of local dedicated volunteers in both India and Europe, in addition to the efforts of our established corps of hardworking people. We expect a very big group of attendees at both of these shows, which adds to the work load for everyone involved.”
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Tags: Accellera, Cadence, CEDA, Dennis Brophy, DVCon, IEEE Standards, Intel, Jill Jacobs, Karen Pieper, Mentor Graphics, Shishpal Rawat, Synopsys, System Verilog AMS standard, SystemC, UPF, UVM, Verilog
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Tuesday, September 9th, 2014
Open source EDA software has been of interest to many, albeit not all, for a number of years. The appeal is intuitive: price point, ability to modify code, ability to weigh in on the design and usability, and so on. The drawbacks are also intuitive: unstable code, insufficient and/or eccentric documentation, ebb and flow of volunteer developers, lack of long-term support for algorithms and code, inability to interact with customers at a detailed enough level to provide software that truly solves problems and supports design.
There are two other drawbacks as well. Open source software is difficult to monetize around and it’s the antithesis of all things proprietary. The EDA industry, however, is profoundly proprietary. End of story?
Surprisingly, no. If you google “Synopsys Open Source”, you’ll get a whole page of links with this intro: “The following open source software are included in one or more Synopsys FPGA software products. Each is a link to information and source code for the respective package. In addition, when required by the open source license agreement, source code or information on acquiring source code is also included with the software product.”
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Tags: Altera, FLOSS, Linus Torvalds, Open Source EDA, Software Freedom Conservancy, Steve Jobs, SWIG, Synopsys, Xilinx, zlib
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Thursday, August 7th, 2014
Ten years ago, numerous hardworking folks in EDAC struggled long and tenaciously to get EDA software removed from a host of restricted-overseas-commerce lists. For those efforts several members of the EDAC community were honored, while sighs of relief were breathed that the industry would not be foolishly restricted by the U.S. Government from exporting their agnostic-to-end-use software.
After all, why would electronic design software have anything to do with communications, avionics, surveillance, ground-based mechanized weaponry, or surface-to-air missile guidance systems, let alone a host of other electronic junk? ‘Just because we made it, doesn’t mean we want it to be used by the bad guys for evil purposes,’ the EDA industry said. And added, ‘Heck, we just produce the stuff. We’re not responsible for how it’s used.’
Of course, that’s not to say that restrictions and guidelines for international commerce have not applied to both EDA and IP. In September of last year, I attended an evening seminar hosted by EDAC that, thanks to the articulate intelligence of Cadence Group Director for Export Compliance and Government Relations Larry Disenhof, outlined in detail the complexities and convoluted guidelines that business folks in the United States must adhere to if they want to stay legal and in business when participating in overseas trade.
It all seemed highly confusing and fraught with the dangers of inadvertently operating outside the lines of what the U.S. Government considered appropriate behavior. Nonetheless, Disenhof offered hope that if companies paid close, close attention to the shifting sands of international relations – pretty much on a daily basis – they would be okay when it comes to obeying the law.
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Tags: Cadence, EDA, EDAC, Larry Disenhof, Mentor Graphics, Moscow, Synopsys, Trade restrictions
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Thursday, July 17th, 2014
Once again EDAC’s Market Statistics Service has released quarterly results for the EDA and IP industries, and once again Mentor Graphics CEO Wally Rhines has taken time to debrief the press on the numbers. When we spoke by phone on July 15th, Rhines started with a qualitative eval of the financial situation in Q1_2014, and moved from there to answer several longer-range questions about autos and today’s troubled world.
“The first quarter of 2014 was good for the industry, but not great,” he said. “With overall growth of 4.6 percent, year over year, it was a good quarter with the highlight being logic design was up a solid 6.6 percent. Other than that, there was not a lot else [remarkable in EDA].”
“Steady, but not glamorous, for Q1?” I asked.
Rhines said, “Yes, steady as she goes in EDA. The IP business, however, was up strongly in Q1, driven up by results from the non-reporting companies, not members of EDAC. We collect public info from non-reporting IP companies such as ARM, Imagination Technologies, MIPS, Rambus [and Synopsys], and we can see overall that the IP business [exhibited] 10-percent growth, quarter over quarter, Q1_2013 to Q1_2014.”
He added, “The bigger trend [visible in] the current MSS report is that all of the world is showing strong [sales], except Japan which is very weak, down 19 percent in contrast to Asia Pacific, which is up 13.5 percent.
“You should also note that North America and Europe are quite strong, up 7 percent or more. Japan is well below those regions as well. Japan used to be a big part of the total [numbers for the industry], substantially larger than the Asia Pacific Region, but now the Pac Rim is twice the size of the Japanese market.”
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Tags: ARM, Cadence, DAC, EDAC, Egypt, El Salvador, Ford, Imagination Technologies, Infineon, Israel, James Buczkowski, MathWorks, Mentor Graphics, Microsoft, MIPS, MSS, Nokia, NXP, Pakistan, Rambus, Renesas Electronics, Synopsys, TI, Wally Rhines
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