Accellera’s PSWG: Realists and Optimists, the lot of them

Mentor Graphics’ Tom Fitzpatrick gave a lunchtime talk at DVCon several weeks ago summarizing recent efforts to build a standard [set of standards?] around portable stimulus for verification. The room was packed with over 200 people and his talk was sufficiently complete, nobody asked any questions.

After his presentation, however, I did hear some comments. Namely that these types of standards are quite complex and difficult to develop. Hence, setting an actual delivery date of January 2017 for Portable Stimulus Standard Version 1 [PSS V1] is quite aggressive and optimistic.

I was not fully informed about Accellera’s Portable Stimulus Working Group [PSWG] prior to Fitzpatrick’s talk, so could not judge whether January 2017 is or is not overly optimistic as a delivery date for the standard. Since DVCon, I have studied the slides and attempted to better understand what this is all about: What is a Portable stimulus and what would a set of standards look like?

To answer those questions, I looked most closely at Slide No. 4, seen here: A Proposed Portable Stimulus Diagram.

Per the diagram, users can be any of the following: system architect, hardware, analog, or software developer, verification engineer, software test engineer, or post-silicon validation engineer. Each of these individuals may create an abstract portable stimulus model with specific syntax to reflect their requisite model parameters, and in so doing declare a use case and/or desired visualization mode.

That ‘model statement’ is then dumped into the design team’s amalgamated design tool set (can remain proprietary despite the ‘standardization’ of the process), which in turn generates a series of tests, targeted at various facets of the verification environment: UML/SysML, SystemC, HVL/UVM, C/C++, and/or AMS.

Reading further into the diagram, this verification environment – the one that’s going to crunch on the generated test sets – can be sitting on one or more platforms: a virtual platform, some sort of simulation engine, an emulation box, an FPGA prototyping platform, and/or a silicon board (whatever that is).

And that’s what I’ve gleaned so far from looking at Slide No.4.

That, and a high-level understanding of what Accellera is calling the ‘scope’ of the Portable Stimulus Standard. It includes middleware, operating systems and drivers, ‘bare-metal’ software, the hardware and software which together constitute an SoC, any type of ‘sub-system’, and/or the IP which is used to build any of the above.

Hmm. There’s a distinct wow factor in all of this, it’s so comprehensive. And it precipitates an unfortunate circling back around to my initial impression upon hearing Tom Fitzpatrick’s talk at DVCon: How can one standard, or set of standards, possibly cover all of this?

This proposed standard, or body of standards, will be so all-inclusive of everything and everyone involved in chip design and verification, it seems almost impossible to assemble – not to mention, be ready for prime time by January of next year.

Clearly, however, many people and companies think it is possible, including Agnisys, AMD, AMIQ EDA, Analog Devices, Breker Verification Systems, Cadence, Cisco, IBM, Intel, Mentor Graphics, NVIDIA, NXP, Qualcomm, Semifore, Synopsys, and Vayavya Labs.

Meanwhile, four companies on the list are vying to have their contributions to the standard be evaluated and accepted: Cadence and Mentor working as a team [promoting a domain-specific language that combines C++ and SystemVerilog intuitions], Breker [has a declarative C++ proposal], and Vayavya [suggesting a complementary syntax to generate register sequences, firmware and driver routines from a canonical/standard hardware/software interface description].

Again, this whole effort seems massive to me. Not just establishing the flow and detailed specs for a Portable Stimulus Standard, but sorting through the politics of corporate posturing/positioning, each party involved hoping to craft a document that most closely matches their internal technology road maps.

Nonetheless, let’s end on a positive note. Intel’s Faris Khundakjie, Mentor’s Tom Fitzpatrick, and Breker’s Tom Anderson – respectively the PSWG Chair, Vice-Chair, and Secretary – are three among many who deserve high praise for having the stamina and enthusiasm to go after this standard.

Listening to Tom Fitzpatrick speak on February 29th, it was clear: It’s not a question of whether the standard can be developed, but if it can be developed within the declared time frame. Which is why Accellera’s PSWG is proving, yet again, that technologists who work on standards are the salt of the earth.

They’re the ones who shun the glamour in favor of getting authentic work done, producing results that help make the world work together. Realists and optimists, the lot of them.

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Tags: Accellera, Accellera PSWG, Agnisys, AMD, AMIQ EDA, Analog Devices, Breker Verification Systems, Cadence, Cisco, DVCon, Faris Khundakjie, IBM, Intel, Mentor Graphics, NVIDIA, NXP, Portable Stimulus Working Group, Qualcomm, Semifore, Synopsys, Tom Anderson, Tom Fitzpatrick, Vayavya Labs

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