GSS: a spirited defense of FDSOI

When it comes to stimulating, it doesn’t get better than stepping out of a session at IEDM in San Francisco to take a conference call from Glasgow. On Tuesday, December 11th, I stepped out of Session 9 and a presentation on spintronics to speak with Dr. Asen Asenov about a different device technology.

Asenov is a 20-year veteran of the University of Glasgow, where he serves as James Watt Professor of Electrical Engineering and heads up the Glasgow Device Modeling Group. He is also founder of Glasgow-based Gold Standard Simulations (GSS), a company that specializes in simulating statistical variability in nano-CMOS devices.

We spoke on December 11th because GSS announced that day the results of research “comparing the differentiation between metal gate first and metal gate last FDSOI [fully-depleted silicon-on-insulation] approaches, and comparing it to equivalent bulk MOSFETs.” Based on that work, the company announced that gate-last technology “offers significant advantages” over gate-first technology for devices built on 32- or 28-nanometer FDSOI, and noted that both nodes “significantly outpace equivalent bulk MOSFETS with respect to low-power SRAM design.”

Asenov elaborated by phone: “In order to deliver low-power applications, the key is to understand that at 28 nanometers, bulk technology is not suitable because of statistical variability. And in moving to 20-nanometer bulk CMOS, we see that things are getting even worse. You’re seeing very small transistors in very high concentrations, which means that statistical variability on-chip is resulting in two unwanted problems.

“First, leakage in the circuit increases, and second, you must have a high-supply voltage on your SRAM. Because SRAM operates with the smallest possible transistors and there is a lot of mismatch, the only way to keep it working at 28 nanometers – and particularly at 20 nanometers – is to keep high-supply voltage, which is bad for low-power circuits and hand-held applications.

“Meanwhile, statistical variability was one of the major factors that moved Intel to FinFETs. FinFETs have the advantage of removing topping from the channel and removing statistical variability, giving you better performance and lower leakage. Now in this world, however, there is one real competitor to FinFET and this is FDSOI.”

Asenov said his group in Glasgow has been working for over 15 years on simulating a range of different types of devices, including measuring amounts of statistical variability, and based on their current work, “STMicro and GobalFoundries are both making commitments to fabricate FDSOI.”

He added, “If you are brave enough to go to FDSOI, it obviously has great potential. It can compete with FinFETS, with similar advantages and a low cost of porting technology.”

Pointing to his statement in the press release, Asenov reiterated: “The breaking news here is that if you can develop a metal gate last 28nm FDSOI technology, you will be able to achieve an astonishing SRAM supply voltage, in the range of 0.5-0.6V.

“Equivalent bulk at 28nm requires approximately 0.9V to secure the reliable operation of large SRAM arrays. Metal gate first FDSOI reduces the minimal SRAM supply voltage (Vcmin) below 0.7V and metal gate last FDSOI at 28nm can reduce Vcmin even further to below 0.5V.”

I asked Asenov about the focus of GSS, that such detailed characterizations are part of a press release.

He said, “GSS has developed a tool chain which allows simulation of technology devices, but also circuits. It’s a tool chain that allows you to accurately simulate and predict state variability in devices, but also to capture accurate statistical models, and allows you to do circuit simulation. We provide these tools, and on the side we also provide services – simulation services, and evaluation of statistical variability, compact model extraction, and PDKs.”

Our conversation ended with this observation: Given that later that day at IEDM, the CEO of GlobalFoundries, Ajit Manocha, was set to keynote regarding current manufacturing issues, it was ironic to be speaking to Prof. Asenov on that very morning.

Whereas the IEEE’s International Electron Devices Meeting now dares to run the gamut of conversation from devices to real-world implementations, Glasgow-based GSS has always spanned that very crucial range of interests and technical capabilities. As IEDM moves to embrace the engineering practicalities of the 21st century, it would appear that GSS is here to welcome them.

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Tags: Asen Asenov, bulk CMOS, FDSOI, FinFETs, GlobalFoundries, GSS, IEDM, Intel, STMicro, University of Glasgow

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