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Posts Tagged ‘veriflabs’

The Second DVCon India Looks Even Better than the First

Thursday, August 20th, 2015

Last week we discussed some of the drivers in the electronics industry influencing the program for the upcoming DVCon India, September 10-11 in  Bangalore. The Technical Program Committee has completed its arduous task of selecting among many worthy proposals for sessions and has posted a near-final program. Today we’d like to highlight some of the most interesting aspects of the packed two days, focusing on sessions that we believe will be a particular draw for those who follow Breker and SoC verification.

There are four conference-wide keynote speeches, from Atul Bhatia (formerly of nSys), Harry Foster of Mentor, Manoj Gandhi of Synopsys, and Vinay Shenoy of Infineon. They will set the tone for the event by discussing the high-level challenges in designing and verifying leading-age semiconductor devices. Nick Heaton of Cadence will keynote the Design and Verification Track (DV) while Pankaj Singh of Infineon and Dr. Sacha Loitz of Continental will give invited talks in the Electronic System Level (ESL) track.

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