Posts Tagged ‘verification IP’
Thursday, November 13th, 2014
In my recent report from the Silicon Valley IP Users Conference, I passed on the prediction that the compound annual growth rate (CAGR) of semiconductor (SIP) is expected to be 12% for the next five years. Clearly there is a growing need for portions of huge SoCs to be pre-designed, pre-verified, and delivered as reusable SIP. This is a trend that started about 20 years ago with the earliest SIP vendors selling libraries and cores for standardized functions along with verification IP (VIP) to support their use.
The IP (SIP and VIP) industry has evolved a lot since then. The most obvious change is that it has been largely consumed by the major EDA companies. Synopsys and Cadence, in particular, have made many acquisitions in this space over the past few years. Some of the price tags have been quite impressive: US$380M for Tensilica, US$315M for Virage, and about the same price for Denali. In this post, I’d like to share some thoughts on the evolution of the IP business.
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Tags: Breker, cache coherency, Cadence, EDA, functional verification, IP, reuse, scenario model, semiconductor IP, SIP, SMIP, SoC verification, Synopsys, TrekApp, verification IP, VIP
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Wednesday, March 19th, 2014
Perhaps by now you’re tired of reading about DVCon, but our last few posts have drawn very good readership so we know that the show is important to the verification-minded engineers who read The Breker Trekker. Another show, or more accurately a series of shows, has strong verification content and draws well from the verification community. We’re talking about the series of Synopsys Users Group (SNUG) events held worldwide to much acclaim from attendees and participating vendors.
According to the SNUG site, Synopsys has 13 shows scheduled annually in Asia, Europe, and North America, drawing nearly 9000 users. That’s a very impressive series of events by any measure and a sign that the EDA market leader invests heavily in educating its users and providing a forum where they can interact among themselves and with Synopsys technical experts. Next week is the 2014 edition of SNUG Silicon Valley, and we want you to know that Breker will be there.
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Tags: Breker, dvcon, functional verification, SNUG, SoC verification, Synopsys, TrekSoC, TrekSoC-Si, verification IP, VIP
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Tuesday, February 4th, 2014
Our last post on the relationship between the Universal Verification Methodology (UVM) and Breker’s technology was very popular. In only a week, it has become the fifth-most-read post in the nine-month history of The Breker Trekker blog. Clearly people are interested in the UVM and what strengths and weaknesses it brings to the ever more complex world of SoC verification.
This week we’d like to continue the discussion with a topic that we did not address last week: how the UVM offers an alternative to running embedded code by replacing one or more of the processors in the SoC with a verification component (VC). Our CEO, Adnan Hamid, addressed this topic in an Electronic Design article last November. We’d like to revisit some of the key points of that article in the context of last week’s UVM discussion
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Tags: Breker, EDA, emulation, functional verification, reuse, scenario model, simulation, SoC verification, system coverage, test generation, TrekSoC, TrekSoC-Si, UVC, uvm, verification component, verification IP, VIP
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Monday, December 30th, 2013
Please allow me to start this post with a sincere wish for all of our readers to have a happy and healthy holiday season. There are many enjoyable activities both sacred and secular this time of year, something for everyone whatever your personal beliefs. I hope that you all have the chance to relax a bit and share some delicious food with family and friends.
I thought about writing a column on the top 5 holiday wishes for verification engineers, but I felt that it would be a bit presumptuous to speak for you. We do work very hard to understand what you need in order to tailor our products to gaps in your verification process and speed up your project. Therefore, I’m going to offer 5 gifts for you, the verification engineer, that are available with Breker’s products. I hope that you like them!
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Tags: applications, Breker, EDA, emulation, functional verification, graph, production software, reuse, scenario model, simulation, SoC verification, system coverage, test generation, TrekSoC, TrekSoC-Si, use cases, uvm, verification IP, VIP
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Tuesday, December 10th, 2013
As you likely know by now, Breker’s primary focus is on verifying SoCs with one or more embedded processors. Sometimes these processors are homogenous, most commonly either the Intel/AMD x86 or ARM architecture. Other SoCs have multiple heterogeneous processors, possibly a diverse mix of cores from x86, ARM, MIPS, ARC, Tensilica, etc.
The trade press devotes a lot of virtual ink to covering the “war” for embedded processor dominance. An article last week made the case for ARM winning. A recent white paper discussed “heterogeneous multi-processing” using ARM’s “big.LITTLE” approach of multiple cores with the same architecture but different performance characteristics. Another article reminded us not to forget about DSPs in the heterogeneous mix. The same could be written about GPUs. So what is Breker’s take on all this?
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Tags: AMD, ARC, ARM, Breker, DSP, EDA, functional verification, GPUs, Intel, IP, Synopsys, Tensilica, verification IP, x86
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Tuesday, November 19th, 2013
In last week’s post, I responded to an article in which Jasper‘s CEO is quoted as saying “formal will dominate verification” and that concluded “at some point in the future, formal will be the default choice for every verification task in the way that simulation/emulation is today.” I challenged this statement, giving examples of SoC verification where I do not believe that formal analysis alone can provide the answer.
Thinking about formal in that way naturally led me to ask the same question about Breker’s technology. Will graph-based scenario models “dominate verification?” At some point in the future, will graph-based scenario models “be the default choice for every verification task in the way that simulation/emulation is today?” As I promised last week, I’ll offer my thoughts on these questions as well.
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Tags: Breker, constrained-random, emulation, formal analysis, functional verification, graph, integration verification, IP, scenario model, SoC verification, TrekSoC, TrekSoC-Si, verification IP
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Tuesday, October 15th, 2013
All of us at Breker are excited as we write this post, since we’ve just made our most important product announcement in several years. We’ve expanded the Breker product line by adding TrekSoC-Si, a brand-new tool that generates multi-threaded, multi-processor, self-verifying C test cases for in-circuit emulation (ICE), FPGA-based prototypes, and actual production silicon. In other words, TrekSoC-Si does for hardware platforms what TrekSoC did for simulation.
We’ll talk more about how TrekSoC-Si works in a moment. But first it’s important to note that both TrekSoC and TrekSoC-Si use the same graph-based scenario models as input to describe the intended behavior of the SoC and provide a test plan. This means that, for the first time in the industry, you can achieve horizontal verification reuse across your entire project schedule, from high-level simulation models all the way through your first chips arriving from the foundry.
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Tags: Breker, EDA, functional verification, graph, reuse, scenario model, SoC verification, Trek, TrekSoC, TrekSoC-Si, verification IP, VIP
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Tuesday, October 8th, 2013
One of the curious aspects of electronics is that most products are specified from the top down but implemented and verified from the bottom up. This is true for system-on-chip (SoC) development as well. As the onset, someone in product marketing specifies a chip that has a specific collection of functionality to meet a specific customer need. The architecture team develops a block diagram that defines the subsystems and perhaps some individual IP blocks as well.
When it comes time to develop the RTL that implements the SoC, designers tend to work from the IP blocks upward. They select commercial IP where it makes sense and develop unique IP when needed. Designers are usually responsible for verifying their own blocks, perhaps with some assistance from verification engineers. There is usually minimal verification of commercial IP unless it has been customized for the SoC project.
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Tags: Breker, functional verification, integration verification, IP, reuse, scenario model, SoC verification, subsystem, use cases, verification IP, vertical, VIP
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