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Posts Tagged ‘static analysis’

Are Verification and Validation Different? Does Anyone Care?

Tuesday, August 25th, 2015

For the most part, the terms “verification” and “validation” are used interchangeably in the electronics industry. However, there are many who argue that these are distinct activities in the development of SoC s and systems, performed at different times in the schedule and usually by different groups of engineers. We refer to ourselves as “The SoC Verification Company” and this is a deliberate choice we made. So we thought that it would be useful to define the two terms as we see them and talk about the similarities and  differences.

This post was inspired by an article from 2010 that our CFO and co-founder Maheen Hamid discovered recently. It opens with the “usual definitions” as follows:

  • “Validation: Are we building the right system?”
  • “Verification: Are we building the system right?”

This seems like a good place to start the discussion.

(more…)




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