Posts Tagged ‘functional verification’
Tuesday, January 7th, 2014
This week’s blog post is inspired by Brian Bailey’s recent article “Making Modeling Less Unpleasant.” I noted with amusement that the link to his article ends with “making-modeling-pleasant” which I suspect was automatically generated from an early draft. So perhaps Brian started with the idea that modeling could be pleasant, but concluded that “less unpleasant” is as good as it can get? Is he too pessimistic? Can modeling actually be pleasant?
It depends in part on what aspect of design or verification modeling we consider. Brian’s primary focus is on system-level models of the design, also called electronic system-level (ESL) models, architectural models, or virtual prototypes. The appeal of a simulatable SoC model fast enough to run compiled code, capable of both functional and performance verification, is easy to understand. There have been many attempts to establish standard approaches, such as transaction-level modeling (TLM), and languages, such as SystemC.
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Tags: Breker, EDA, formal analysis, functional verification, graph, SoC verification, system coverage, test generation, use cases, uvm
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Monday, December 30th, 2013
Please allow me to start this post with a sincere wish for all of our readers to have a happy and healthy holiday season. There are many enjoyable activities both sacred and secular this time of year, something for everyone whatever your personal beliefs. I hope that you all have the chance to relax a bit and share some delicious food with family and friends.
I thought about writing a column on the top 5 holiday wishes for verification engineers, but I felt that it would be a bit presumptuous to speak for you. We do work very hard to understand what you need in order to tailor our products to gaps in your verification process and speed up your project. Therefore, I’m going to offer 5 gifts for you, the verification engineer, that are available with Breker’s products. I hope that you like them!
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Tags: applications, Breker, EDA, emulation, functional verification, graph, production software, reuse, scenario model, simulation, SoC verification, system coverage, test generation, TrekSoC, TrekSoC-Si, use cases, uvm, verification IP, VIP
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Tuesday, December 17th, 2013
With due apologies to Barbra Streisand, the topic of today’s blog post is the verification of SoC memories and memory subsystems. Once upon a time, memories were considered just about the easiest design structure to verify. A simple automated test doing “walking 1s” and “walking 0s” supplemented by some random reads and write to random addresses with random data seemed to be good enough.
“Can it be that it was all so simple then? Or has time re-written every line?” Actually, it really was that simple back then. But a lot of changes in memory subsystems have come along to complicate matters: memory regions, caches, multi-processor designs, shared memory, complex memory maps, etc. Verification of memories today is much more challenging, with many corner cases to be exercised, but it’s an essential part of the overall SoC verification effort.
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Tags: Breker, buffer, cache, coherency, constrained-random, emulation, functional verification, graph, memories, memory map, scenario model, streisand, system coverage, TrekSoC, TrekSoC-Si
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Tuesday, December 10th, 2013
As you likely know by now, Breker’s primary focus is on verifying SoCs with one or more embedded processors. Sometimes these processors are homogenous, most commonly either the Intel/AMD x86 or ARM architecture. Other SoCs have multiple heterogeneous processors, possibly a diverse mix of cores from x86, ARM, MIPS, ARC, Tensilica, etc.
The trade press devotes a lot of virtual ink to covering the “war” for embedded processor dominance. An article last week made the case for ARM winning. A recent white paper discussed “heterogeneous multi-processing” using ARM’s “big.LITTLE” approach of multiple cores with the same architecture but different performance characteristics. Another article reminded us not to forget about DSPs in the heterogeneous mix. The same could be written about GPUs. So what is Breker’s take on all this?
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Tags: AMD, ARC, ARM, Breker, DSP, EDA, functional verification, GPUs, Intel, IP, Synopsys, Tensilica, verification IP, x86
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Tuesday, November 26th, 2013
The Breker Trekker has been publishing for about seven months now, with 32 posts to date, so running just about once a week. When we started, we committed a new post every two weeks so we’ve been running well ahead of our own expectations. We’re very happy with the growth of our readership and we’d like to take this chance to thank every one of you reading this.
Frankly, we have not been as successful at driving an ongoing dialogue via comments. We’ve had a few comments here and there but not nearly as many as we would like to see. So for this week’s post we’re trying something different: posing a question directly to our readers and heartily encouraging all of you to share your thoughts by leaving a comment at the bottom. Today’s topic: which conferences and trade shows do you find most useful?
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Tags: arrm techcon, Cadence, CDNLive, conference, dac, dvcon, EDA, functional verification, SNUG, Synopsys
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Tuesday, November 19th, 2013
In last week’s post, I responded to an article in which Jasper‘s CEO is quoted as saying “formal will dominate verification” and that concluded “at some point in the future, formal will be the default choice for every verification task in the way that simulation/emulation is today.” I challenged this statement, giving examples of SoC verification where I do not believe that formal analysis alone can provide the answer.
Thinking about formal in that way naturally led me to ask the same question about Breker’s technology. Will graph-based scenario models “dominate verification?” At some point in the future, will graph-based scenario models “be the default choice for every verification task in the way that simulation/emulation is today?” As I promised last week, I’ll offer my thoughts on these questions as well.
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Tags: Breker, constrained-random, emulation, formal analysis, functional verification, graph, integration verification, IP, scenario model, SoC verification, TrekSoC, TrekSoC-Si, verification IP
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Wednesday, November 13th, 2013
Today’s post is prompted by a recent article on SemiWiki in which Jasper Design Automation’s CEO Kathryn Kranen is quoted as saying “formal will dominate verification.” There is a nice set of metrics from Jasper’s recent User Group meeting showing their impressive growth in revenue, logos, users, and licenses as supporting evidence for formal’s increasing footprint. The article concludes by stating “at some point in the future, formal will be the default choice for every verification task in the way that simulation/emulation is today.”
That made me sit up and take notice. Before joining Breker, I spent the previous 12 years of my career focusing on formal analysis, about six years full-time and the rest as one component of a wider suite of verification products I managed. I’m a big fan of formal, but I don’t think that I can comfortably predict that it will “dominate” verification. Let me share my thoughts.
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Tags: analysis, Breker, emulation, formal, FPGA, functional verification, graph, IP, jasper, Kranen, scenario model, simulation, SoC verification, test generation, TrekSoC, TrekSoC-Si
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Monday, November 4th, 2013
Emulation got its start in the late 1980s. As an early employee of the pioneering company in emulation, Quickturn Design Systems, I remember the enthusiasm created by the promises of the technology and the challenges that came with its delivery. It is not an exaggeration to state that many of the early adopters failed to get a decent ROI on their emulation investment because of finicky software or unreliable hardware.
However, emulation has come a long way in terms of performance, ease-of-use, reliability, and pricing. This maturity enables SoC design teams all over the world to make emulation a key component of their verification arsenal. The three major suppliers of emulation are enjoying steady growth and almost unstoppable momentum due to the increasing complexity of SoCs.
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Tags: Breker, emulation, functional verification, integration verification, Quickturn, SoC verification, test cases, TrekSoC, TrekSoC-Si
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Monday, October 28th, 2013
Over the last couple of decades, vendor-specific conferences have complemented and in some markets even supplanted general industry events. Intel, Microsoft, Sun/Oracle, Apple, and many other companies have had huge, successful shows year after year. Perhaps it’s a sign of a certain level of maturity when a company has the resources to hold its own event and the appeal to attract a large crowd.
In the world of EDA (and IP, and embedded systems), ARM is certainly one of the biggest recent success stories. As the company has grown, its small technical events have evolved into a major show now known as ARM TechCon. Breker will be both speaking and exhibiting at this week’s event in Santa Clara, just down the road from Breker’s headquarters in San Jose.
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Tags: ARM TechCon, Breker, EDA, functional verification, SoC verification, TrekSoC, TrekSoC-Si
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Monday, October 21st, 2013
Breker customers have surely noticed that the quantity and quality of our product documentation have taken a huge leap in the last six months or so. This is due to the Herculean efforts of Bob Widman, a well-known documentation, training, and applications expert in the EDA industry. He has been working with Breker for most of this year and the results speak for themselves. We’re pleased that Bob has contributed the following guest post on the importance of documentation:
Why does a company provide documentation with its product? The typical answer is that the customer expects it. Often overlooked is how the process of creating the documentation has a positive impact on the product and the company that is developing it.
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Tags: Breker, documentation, functional verification, integration verification, manuals, SoC verification, startup, TrekSoC, TrekSoC-Si
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