As I hoped, my recent post challenging Jasper Design Automation’s statement that “formal will dominate verification” has drawn very good readership and generated some stimulating industry discussions. Today, Joe Hupcey III from Jasper responds and offers more ammunition for their claims of dramatic recent advances in the power and usability of formal technology:
Thanks to the folks at Breker for the comments and analysis in your post asking “Will Formal Really Dominate Verification?” in reference to Jasper’s recent assertion of formal’s ascendancy. As your thoughtful post acknowledges, verifiers are seeing formal starting to take over block and unit level verification, as well as select system-level applications. Indeed, the industry has seen this movie twice before – specifically, the growth of emulation into the mainstream and again with constrained-random simulation.
