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Posts Tagged ‘cache coherency’

Some Thoughts on SIPs, VIPs, and SMIPs

Thursday, November 13th, 2014

In my recent report from the Silicon Valley IP Users Conference, I passed on the prediction that the compound annual growth rate (CAGR) of semiconductor (SIP) is expected to be 12% for the next five years. Clearly there is a growing need for portions of huge SoCs to be pre-designed, pre-verified, and delivered as reusable SIP. This is a trend that started about 20 years ago with the earliest SIP vendors selling libraries and cores for standardized functions along with verification IP (VIP) to support their use.

The IP (SIP and VIP) industry has evolved a lot since then. The most obvious change is that it has been largely consumed by the major EDA companies. Synopsys and Cadence, in particular, have made many acquisitions in this space over the past few years. Some of the price tags have been quite impressive:  US$380M  for Tensilica, US$315M for Virage, and about the same price for Denali. In this post, I’d like to share some thoughts on the evolution of the IP business.

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