Posts Tagged ‘cache coherency’
Tuesday, June 30th, 2015
Last week on The Breker Trekker, we discussed the resurgence of interest in EDA tools in the cloud. Like our first post on the topic two year’s ago, last week’s entry was very popular. Clearly this is a topic of interest to both our regular and occasional readers. Two more announcements regarding EDA in the cloud also surfaced during the recent Design Automation Conference (DAC), so it does seem as if there is more effort going toward finding a technically and financially successful industry solution.
Last week we summarized five barriers that have helped prevent cloud-based EDA from achieving mainstream adoption:
- The EDA vendor’s effort to port to a cloud-based platform
- Worries about GUI and interactive responsiveness
- Ability to support users of cloud-based tools
- Lack of an established, proven business model
- Concerns over security of the design and verification data in the cloud
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Tags: Accellera, Breker, cache coherency, cloud, cloud computing, EDA, functional verification, graph, graph-based, IP, low power, portable stimulus, scenario model, simulation, SoC verification, TrekApp, use cases, uvm, VIP
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Wednesday, June 24th, 2015
It has been almost exactly two years since we discussed the possibility of EDA tools in the cloud here on The Breker Trekker. The post was popular then, and it remains so. In fact, of the more than 100 posts we’ve published, our cloud post remains the second most read. This week, the recent news that IBM will make its EDA tools available in the cloud through a partnership with SiCAD brought cloud computing back to the forefront. Let’s discuss what has changed–and what hasn’t–in the past two years.
The idea of users being able to run EDA tools as leased enterprise software on remote machines has been around for years, well before the term “the cloud” was widely used. Synopsys invested a great deal of time and effort into its DesignSphere infrastructure, initially more of a grid application than a cloud solution as we use the term today. But the difference is not very important; the key concepts are the same and they represent a major departure from the time-tested model of customers “owning” EDA tools and running them in-house.
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Tags: Accellera, Breker, cache coherency, cloud, cloud computing, EDA, functional verification, graph, graph-based, IP, low power, portable stimulus, scenario model, simulation, SoC verification, TrekApp, use cases, uvm, VIP
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Wednesday, June 17th, 2015
As we have discussed before, we have followed the lead of other EDA vendors by packaging aspects of our advanced verification technologies into pushbutton applications (apps). The first in this product line, our Cache Coherency TrekApp, has been very popular since its introduction last year. As we have covered in depth, this is due in part to the trend of large chips becoming multiprocessor SoCs with multi-level caches. The sudden escalation of cache coherency verification from the CPU developer to the system integrator created strong demand for our nicely bundled solution.
There are many other trends ongoing and emerging in the SoC industry, and we have a long list of ideas for possible TrekApps to help address the challenges that are arising. We would like your help in prioritizing our development efforts. We have established a survey listing ten TrekApps under consideration. Please simply check off the ones of most interest to you by midnight Pacific time on June 30. All submissions will be entered into a drawing for a $50 Amazon.com gift card.
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Tags: ARM, Breker, cache coherency, clock domains, EDA, Ethernet, functional verification, graph, graph-based, IP, low power, PCIe, portable stimulus, scenario model, security, simulation, SoC verification, TrekApp, USB, use cases, uvm, VIP
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Thursday, June 11th, 2015
Last week we looked forward to the 52nd edition of the annual Design Automation Conference (DAC), held this week at Moscone Center in San Francisco. Today we look back at the past three days and all of the activity at the show. It was a very busy time for Breker as usual, but there were some special aspects this year that we’d like to mention. We also want to thank the many customers, prospects, colleagues, and even competitors who joined us at various times for provocative discussions and plenty of social networking. As always, we invite you to add your comments on DAC and what you thought about the show.
Overall, the exhibition floor seemed lively for most of the time. We frequently had multiple visitors in our booth, asking questions and watching demos. We focused on two aspects of our Trek product line: immediate availability of portable stimulus and pushbutton verification of cache coherency. We saw lots of interest in both topics and it’s hard to say which drew more attention. Our suite was booked for most of the time, with customers receiving updates from Breker and prospects discussing their verification challenges and how we might be able to help them.
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Tags: Accellera, Altera, Breker, cache coherency, dac, Design Automation Conference, EDA, functional verification, graph, graph-based, IBM, Moscone, portable stimulus, San Francisco, scenario model, simulation, SoC verification, TrekApp, uvm, VIP
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Tuesday, June 2nd, 2015
We have less than a week to go before the most important event for EDA vendors and users: the annual Design Automation Conference (DAC). The show returns to Moscone Center in San Francisco, which has played host many times over the years. As one of the most popular tourist destinations in the world, San Francisco is a great draw for out-of-towners but also just a short trip from Breker’s headquarters in the heart of Silicon Valley. The combination of a strong peer-reviewed technical conference and a busy exhibition floor is unbeatable, making this a must-attend event for many in our industry.
When the technical program first came out two months ago, we posted about some of the interesting changes made this year. There are some innovative additions to the program, including keynotes from non-EDA vendors, “sky talks” from industry experts, a major focus on the Internet of Things (IoT), and tracks for such important topics as automotive electronics, IP, and security. The popular Designer Track returns with case studies from real users, and there are plenty of deep technical papers for those who spend their days coding algorithms and optimizing data structures. At least eight sessions have significant verification content.
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Tags: Accellera, Breker, cache coherency, dac, Design Automation Conference, EDA, functional verification, graph, graph-based, IBM, Moscone, portable stimulus, San Francisco, scenario model, simulation, SoC verification, TrekApp, uvm, VIP
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Tuesday, March 10th, 2015
Last May, I published two blog posts on the presentations made at a “Decoding Formal Club” event hosted by the smart folks from Oski Technology at the Computer History Museum in Mountain View. With everything else going on, I didn’t manage to make it to another of their regular meetings until last week. The first event of 2015 was very interesting, so again I’m returning to the popular topic of formal analysis and playing reporter. The line between media and blogging is rather thin these days anyway.
This edition of Decoding Formal featured three talks, one an end-user case study and the other two instructional in nature from well-known formal experts. I found all three worthwhile and will do my best to communicate some of the main points made. I also have to mention the final presentation, more a performance than a talk, by the inimitable and irrepressible Clifford Stoll. Lately he’s been manufacturing and selling Klein bottles, which you may remember from a geometry teacher trying to mess with your mind.
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Tags: Accellera, Breker, cache coherency, constraints, EDA, formal, functional verification, graph-based verification, oski, portable stimulus, properties, scenario model, SoC verification, standards, Trek, TrekApp, TrekSoC
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Thursday, March 5th, 2015
In last week’s blog post on The Breker Treker we previewed this week’s Design and Verification Conference (DVCon) in San Jose, the leading industry event for verification professionals. We had a really good time there, finishing up just this afternoon. We always enjoy DVCon, but this week was even more fun than usual. We met attendees from an amazing range of companies designing SoCs, from simple microcontrollers to some of the largest FPGAs and custom chips on the planet.
Three aspects of the show really stood out: intense interest in cache coherency verification, considerable curiosity about the Accellera Portable Stimulus Working Group (PSWG), and the number of people who started the conversation with “I’ve heard good things about Breker from a colleague” or “I was told that I really need to check you out.” Let’s discuss what each of these trends means for the industry and speculate about the impact on Breker.
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Tags: Accellera, ARM, Breker, cache coherency, Carbon, CPAK, DesignCon, dvcon, DVCon Europe, DVCon India, EDA, functional verification, integration verification, IP, portable stimulus, SoC verification, standards, Trek, TrekApp, TrekSoC, verification IP, VIP
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Tuesday, February 24th, 2015
Most of the time when we blog about upcoming conferences, report live from an ongoing show, or summarize one that’s just finished, we see a significant spike in readership. Clearly our followers want to keep up with what’s happening in trade shows, conferences, and other industry events. It may also be the case that tighter travel budgets have reduced the ability to attend conferences in person, driving all the more interest in reading the news from the field. A few weeks ago, we discussed DesignCon and explained how it had evolved to include almost no verification content.
Next week is the annual Design and Verification Conference (DVCon) in San Jose, an event that we have covered in considerable detail in several popular posts in the past. As we have discussed, this conference has become the main way to keep up on what’s happening in the ever-changing world of functional verification. We encourage you to check out their Web site and the complete program. The topics include the UVM, SystemVerilog, SystemC, code generation, multi-language, mixed-signal, formal techniques, coverage metrics, and low-power verification.
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Tags: Accellera, Breker, cache coherency, Carbon, CPAK, DesignCon, dvcon, EDA, functional verification, integration verification, IP, portable stimulus, standards, Trek, TrekApp, TrekSoC, verification IP, VIP
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Thursday, February 5th, 2015
Two recent blog posts discussed what you should run when you first map your system-on-chip (SoC) design into an emulation platform and when you have your first fabricated chips from the foundry in your bring-up lab. We pointed out that trying to boot an operating system and run applications should not be the first step because production software is not designed to find and debug lingering hardware design errors. We recommended running the multi-threaded, multi-processor, self-verifying C test cases generated and optimized for hardware platforms by our TreSoC-Si product.
As you may know, TrekSoC uses the same graph-based scenario models as TrekSoC-Si, but optimizes the generated test cases for virtual prototypes, simulation, and simulation acceleration. In this post, we ask a similar question: what should you run in simulation when you first have the RTL for your SoC assembled and ready to be verified? Of course our answer will be the test cases generated by TrekSoC. However, there are some advantages of simulation over hardware platforms that foster a more extensive methodology for verification with Breker’s products.
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Tags: acceleration, Breker, bring-up lab, cache coherency, EDA, emulation, functional verification, graph, graph-based, portable stimulus, scenario model, simulation, SoC verification, test generation, TrekApp, TrekSoC-Si, use cases
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Tuesday, November 18th, 2014
In last week’s blog post, we talked about the emergence of the commercial IP industry and shared some personal experiences. Although Breker is an EDA company and not known for IP products, we intersect with semiconductor IP (SIP) and verification IP (VIP) in important ways as we work with our customers. We’re also starting to offer our own scenario model IP (SMIP) as part of accelerating and improving verification even more. We’d like to expand on these topics in today’s post.
We have few if any customers or prospective customers who don’t use commercial VIP in their testbenches. After all, if you’re designing a standard interface you want the best verification possible that you’re meeting the standard. A VIP model that’s been used by dozens or hundreds of other projects serves as a pre-silicon “plugfest” where you get to verify your implementation of the standard against what others have done. Now that the Universal Verification Methodology (UVM) is nearly ubiquitous, most VIP is developed in a fairly consistent manner.
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Tags: Breker, cache coherency, EDA, functional verification, graph, IP, reuse, scenario model, semiconductor IP, SIP, SMIP, SoC verification, TrekApp, TrekSoC, TrekUVM, verification IP, VIP
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