Portable Stimulus Was Front and Center at this Year’s DVCon

We’ve just returned from our most important trade show of the year: the Design and Verification Conference and Exhibition (DVCon) in San Jose. Sure, DAC is a bigger show, but it covers all of EDA and so lacks the front-end digital focus of DVCon. We previewed the event over our last few blog posts and today we’d like to summarize what happened and make a prediction or two about how this particular DVCon will affect the industry.

The biggest news for us was that portable stimulus seemed to be on everyone’s lips this year. Many of the engineers who stopped by to visit our booth had heard the term and were aware that the Accellera Portable Stimulus Working Group (PSWG) is developing a standard. If they didn’t know what portable stimulus was, they almost surely knew by the end of the show.

Monday was Leap Day and Accellera Day, featuring tutorials on standards developed by the organization. Portable stimulus is not far enough along for a tutorial yet, but during an Accellera-sponsored lunch Vice-Chair Tom Fitzpatrick of Mentor presented a concise summary of where the PSWG stands on our path to a standard. The group is considering a proposal from Breker using C++ for scenario model specification and a proposal for a new language being championed by Cadence and Mentor. A decision is likely in the near future, and Accellera is encouraging more input and participation from user companies.

The highlight of the show for us came on Tuesday morning, when Raja Pantangi from Cavium co-presented “Using Portable Stimulus to Verify Cache Coherency in a Many-Core SoC” with Breker CEO Adnan Hamid. Adnan discussed why cache coherency is such a challenging verification problem and Raja described a recent project in which Cavium needed to verify three SoCs containing a total of 144 CPU cores in the bring-up lab.

Cavium used our Cache Coherency TrekApp and TrekSoC-Si to verify full cache coherency across 96 ARM cores in two of the chips while generating PCI Express (PCIe) traffic on 48 MIPS cores in the third chip. All test cases generated by our tools were self-checking and multi-threaded, with the CPUs interacting and interleaving. Cavium says that their team “regards automatically generated test cases as essential for cache coherency verification” and that they are now running some test cases in simulation and emulation as well as in silicon.

Our booth was very busy during the three exhibit sessions, with many visitors saying that they had seen the Cavium talk and were eager to learn more about Breker. We would like to extend our sincerest thanks to Cavium for being willing to share their story. Attendees at shows such as DVCon really appreciate hearing project results directly from other users, and this paper in particular is likely to have an impact in the wider verification community.

Adnan also participated in a panel on“Redefining ESL”on Wednesday morning. Several panelists made the point that electronic system-level (ESL) is a broad term covering virtual prototypes for software development, architectural modeling, high-level synthesis, and more. Given the breadth of this discussion, we’ll schedule a future blog post to summarize the panel and discuss ESL in general. Adnan focused on verification reuse from ESL to RTL simulation and beyond, noting that this is part of the Accellera vision for portable stimulus.

Mentor mentioned portable stimulus in their keynote address by CEO Walden (Wally) Rhines on Tuesday, and Cadence featured a panel on the topic at their sponsored lunch on Wednesday. The panel was mostly just a summary of why portable stimulus is so important and timely, although a question from the floor correctly pointed out that most of the panelists were focusing on stimulus with almost no mention of results checking or coverage. Any useful test case, of course, requires all three components.

Indeed, portable stimulus was the hot topic for DVCon this week. The timing was perfect, given that PSWG is getting close to a decision on the baseline for the standard and the Cavium talk showed that the Accellera vision is already reality with Breker’s solutions. We invite your own thoughts on DVCon if you attended, as well as your questions or comments on any of the topics we’ve discussed. As always, thank you for following us.

Tom A.

The truth is out there … sometimes it’s in a blog.

Tags: Accellera, application, Breker, bring-up lab, cache coherency, Cadence, Cavium, dvcon, emulation, ESL, FPGA, functional verification, graph, graph-based, mentor, multi-SoC, node coverage, path coverage, portable stimulus, prototyping, PSWG, realistic use case, scenario model, simulation, SoC validation, SoC verification, system-on-chip, test case generator, test cases, TrekApp, TrekSoC-Si, Universal Verification Methodology, use-case coverage, uvm

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