Frontiers of Microprocessor Test and Verification

In last week’s blog post, I reported from the recent 16th International Workshop on Microprocessor Test and Verification (MTV) in Austin. I focused mostly on the panel “Portable Stimulus and Testbenches – Possibilities or Wishful Thinking?” that included representatives from ARM, Cadence, Mentor, Synopsys, Freescale (now NXP), and Breker (yours truly). The panel was most enjoyable, but only one of several highlights for me at MTV.

This week, I’d like to touch briefly on some of the talks and topics on the technical program that caught my ear. These reflected a number of research frontiers for verification as well as several real-world case studies of SoC design projects tackling tough verification challenges. Perhaps the best moment for me was hearing Altera, one of our customers, describe how they used our products successfully on a recent design.

A keynote address by Processor Li C Wang from the University of California at Santa Barbara on “Big Data Analytics for Validation and Test” was intriguing. He talked about mining the huge quantity of data generated by verification tests to extract information related to unique failure modes. The concept of looking for signatures that tie a large number of failed tests to a single cause is familiar to verification teams; the possibility of completely automating this process is certainly attractive.

As I expected, there were several interesting presentations on formal analysis. I’m a big fan of using puzzles such as Sudoku or Rubik’s Cube to show the power of a formal constraint solver. Jeremy Ridgeway from Avago discussed “Performance of a SystemVerilog Sudoku Solver with VCS” by showing the results of different approaches to writing constraints. In addition, AMD talked about using formal to verify an IP block responsible for reset and NVIDIA focused on formally determining unreachable coverage goals.

Given Breker’s product space, I was particularly interested in talks dealing with automated test generation. Researchers from the Institute for System Programming at the Russian Academy of Sciences (ISP RAS) presented a system to generate test programs for ARM memory management units (MMUs). ARM described how to enhance efficiency of random instruction sequence (RIS) generation tools. They reported that intelligent use of coverage feedback resulted in a 10x improvement for some parts of their verification plan.

For the related topic of automatic coverage closure, engineers from Cadence outlined a new way to improve constrained-random convergence using coverage-driven distribution with their e language. Other talks focused on different aspects of verification technology, including virtual platforms, emulation, debug analysis, and bug triage. There were also several sessions on security, mostly at the software level so I didn’t come away with any clever ideas for better verification of hardware security features.

The Altera talk on “Verification of a Cache Coherent system with an A53 cluster using ACE VIP with Graph Based Stimulus” was given by Perry Wobil. The use of the term “graph” suggests that Breker might have been involved, and in fact this project used our TrekSoC and Cache Coherency TrekApp products as a key part of the verification process. Cache coherency has been the most popular application of our technology in the past year or two, and the Altera case study demonstrates why.

The design they verified is complex, including a cluster of four ARM Cortex-A53 processors, each with its own level 1 (L1) cache and MMU, and a shared L2 cache. This cluster ties to a cache coherent interconnect that implements the ARM AXI Coherency Extensions (ACE) protocol. Also hooked to this interconnect is a verification IP (VIP) model of an ACE master with its own cache, representing an additional coherent processor implemented in programmable logic.

Using the pre-built cache coherency graphs from our TrekApp, the Altera team was able to use TrekSoC to generate C test cases that ran on all four processors in simulation and generate testbench UVM transactions to and from the ACE VIP component. The code running on the processors is coordinated with the testbench transactions by the TrekBox run-time component. The result was a high volume of coherent traffic types from different masters with collisions of coherent transactions on select cache lines.

Altera reported that “this environment has increased the quality of coherent traffic, the quantity of traffic and improved the ability to debug the complex traffic that is the nature of cache coherent systems.” There are many more aspects to their story, so I will plan a future blog post or white paper to fill in the details. For now, let me thank Altera for their excellent presentation, thank the MTV organizers for inviting me to join the panel, thank you for reading, and wish everyone a happy holiday season.

Tom A.

The truth is out there … sometimes it’s in a blog.

Tags: Accellera, AMD, ARM, austin, Avago, Breker, Cadence, EDA, FPGA, Freescale, functional verification, graph, graph-based, mentor, MTV, node, NVIDIA, portable stimulus, PSWG, scenario model, simulation, SoC verification, Sudoku, Synopsys, test generator

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