Report from the 16th MTV Workshop

Do you want to hear all the behind-the-scenes dirt from a workshop on the future of the MTV cable channel? Well, you’ll have to look elsewhere. “MTV” in this case means the International Workshop on Microprocessor Test and Verification, which celebrated its 16th incarnation in Austin two weeks ago. Although the name of the workshop has officially expanded to “Microprocessor and SOC Test and Verification” rest assured that the delightfully ambiguous abbreviation “MTV” will remain.

This was only my second time at this event, but I wish that I had been able to attend more. The setting is the top floor of the Hyatt Regency, with great views of Lady Bird Lake (formerly Town Lake) and downtown Austin. However, I noticed that recent high-rise construction has now blocked the sight of the Texas State Capitol from the hotel. The view might be distracting if not for the fact that the technical committee put together an interesting and diverse program, including a panel on portable stimulus.

Since this panel was the main reason for my attendance this year, I’ll cover that first. Harry Foster from Mentor moderated, co-organized, and likely came up with the intriguing title “Portable Stimulus and Testbenches – Possibilities or Wishful Thinking?” Across the six panelists, there was an interesting split between two sets of three. I chose to focus on the higher-level message, reminding the attendees that both vertical (IP to SoC) and horizontal (simulation to silicon) reuse were explicit goals for the standard being develop by the Accellera Portable Stimulus Working Group (PSWG).

In reference to the panel title, I pointed out that there was no “wishful thinking” about portable stimulus at all. Breker’s customers have been automatically generating portable stimulus, results checking, and coverage for years. I mentioned one company who starts building graph-based scenario models for their IP blocks and combines them for a top-level graph of nearly a million nodes. I also described how another customer generates interacting test cases for nearly 100 embedded processors and runs them on real silicon in the bring-up lab.

Mike Stellfox from Cadence voiced similar thoughts about portable stimulus working today, so the question is not whether it is possible but rather what the upcoming standard should encompass. Daniel Schostak from ARM, the only one of the six panelist companies not active in the PSWG, discussed some of the requirements that a portable stimulus solution or standard would have to satisfy. I thought that it was valuable to have a non-Accellera perspective on this topic.

In contrast, Monica Farkash from Freescale (now NXP), Tom Fitzpatrick from Mentor, and Hillel Miller from Synopsys put more emphasis on the inner workings of the PSWG. All three are active participants and so are involved in the deep discussions on whether the standard should leverage an existing language, define a new language, or craft some sort of combination solution. This is an important issue and one that I have discussed in this blog several times, but perhaps too parochial for the MTV audience.

The panel was followed by some provocative questions from both the moderator and the attendees. One thing that was clear from the questions is that the term “portable stimulus” confuses people. As I mentioned in my introductory remarks and echoed in answering the questions, the Accellera standard will not be about writing bits that can run on every level (IP to SoC) and every verification platform. Rather, the standard is defining a single abstract model from which vendor tools can generate appropriate bits for the different target environments.

It was also apparent from the questions that the approach of portable stimulus and test cases satisfies a real need in the SoC community. Verification engineers are having to do a lot of re-coding of testbench components as they move from IP to full chip. Embedded programmers essentially start from scratch when a hardware platform such as in-circuit emulation (ICE) and FPGA prototypes comes into the picture. When the SoC arrives from the foundry, the silicon validation team also does a lot of new work to test out parts of the chip before trying to run production software.

Unifying and automating all this verification and validation activity with a single abstract graph-based model has clear value for existing users and the approach will propagate quickly once a standard is in place. I came away from MTV more certain then ever that Breker is on the right path. The program also included an excellent talk by Altera on their use of our TrekSoC tool as well as several other topics of interest. I will continue talking about MTV for another post or two so that I do it justice. As always, please comment if you have any questions or opinions.

Tom A.

The truth is out there … sometimes it’s in a blog.

Tags: Accellera, ARM, austin, Breker, Cadence, EDA, emulation, FPGA, Freescale, functional verification, graph, graph-based, horizontal reuse, mentor, MTV, node, portable stimulus, PSWG, scenario model, silicon, simulation, SoC verification, Synopsys, test generator, vertical reuse

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