The Second DVCon India Looks Even Better than the First

Last week we discussed some of the drivers in the electronics industry influencing the program for the upcoming DVCon India, September 10-11 in  Bangalore. The Technical Program Committee has completed its arduous task of selecting among many worthy proposals for sessions and has posted a near-final program. Today we’d like to highlight some of the most interesting aspects of the packed two days, focusing on sessions that we believe will be a particular draw for those who follow Breker and SoC verification.

There are four conference-wide keynote speeches, from Atul Bhatia (formerly of nSys), Harry Foster of Mentor, Manoj Gandhi of Synopsys, and Vinay Shenoy of Infineon. They will set the tone for the event by discussing the high-level challenges in designing and verifying leading-age semiconductor devices. Nick Heaton of Cadence will keynote the Design and Verification Track (DV) while Pankaj Singh of Infineon and Dr. Sacha Loitz of Continental will give invited talks in the Electronic System Level (ESL) track.

There are ten tutorials across the two tracks, covering such standards as SystemVerilog, SystemC, the UVM, TLM2.0, and IP-XACT. Two tutorials devoted to debug show how important this topic has become. Most interesting to us, it is clear that portable stimulus and the Accellera Portable Stimulus Working Group (PSWG) standardization effort will be hot topics. Breker is presenting a joint tutorial on “Leveraging Portable Stimulus across Domains and Disciplines” together with colleagues from Mentor Graphics and Vayavya.

Panels are usually some of the liveliest sessions at any conference, since they offer the audience the chance to interact directly with the speakers. The three panel topics are very impressive, spanning the Internet-of-things (IoT), new verification flows, and the ESL continuum. Even the technical talks this year sound highly topical and eminently practical. These are not dry, esoteric lectures from academia; everyday chip architects, designers, and verification engineers will be sharing their knowledge directly with the attendees.

Portable stimulus will be front and center in the program. The very first technical session slot features long-time Breker users from IBM on “Walking the Graph” and we’re looking forward to that paper. Mentor will also discuss the virtues of graphs for network packet header generation, while our friends from VerifLabs will present approaches for coverage closure. With these three talks all in the same session, it is a must-see for anyone interested enough in SoC verification to be reading this blog.

There are also talks on the UVM, emulation, CPU modeling, virtual prototypes, mixed-signal verification, testing driver software, formal clock-domain crossing (CDC) checks, and many more topics. There’s even a session on VHDL, which is getting some new life via the Open Source VHDL Verification Methodology (OS-VVM) packages. As a bonus, there are more than a dozen posters being presented in an informal format encouraging interaction between authors and attendees.

Last but certainly not least, DVCon India offers many chances for networking and stimulating interaction with a bunch of smart engineers. These include lunch, tea time, and a special gala dinner on Thursday night celebrating the tenth anniversary of the standardization of SystemVerilog and the recent transfer of the UVM from Accellera to the IEEE. A wide range of vendors will have booths open in exhibit areas throughout both days. Breker will have a booth there, and we will be glad to discuss why we’re the leaders in the emerging portable stimulus space.

So, we most cordially invite you to visit the second annual DVCon India. Last year’s inaugural show was informative, busy, and fun. We believe that this year will be even bigger and better. Please join us, stop by our booth to say hello, and don’t miss our tutorial and related talks. We look forward to seeing you in Bangalore!

The truth is out there … sometimes it’s in a blog.

Tom A.

Tags: Accellera, Breker, CVC, dvcon, DVCon India, EDA, functional verification, graph, graph-based, IBM, mentor, portable stimulus, PSWG, scenario model, simulation, SoC verification, software-driven verification, test generator, Universal Verification Methodology, uvm, veriflabs, VIP

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