Please Help Us Choose Our Next TrekApp

As we have discussed before, we have followed the lead of other EDA vendors by packaging aspects of our advanced verification technologies into pushbutton applications (apps). The first in this product line, our Cache Coherency TrekApp, has been very popular since its introduction last year. As we have covered in depth, this is due in part to the trend of large chips becoming multiprocessor SoCs with multi-level caches. The sudden escalation of cache coherency verification from the CPU developer to the system integrator created strong demand for our nicely bundled solution.

There are many other trends ongoing and emerging in the SoC industry, and we have a long list of ideas for possible TrekApps to help address the challenges that are arising. We would like your help in prioritizing our development efforts. We have established a survey listing ten TrekApps under consideration. Please simply check off the ones of most interest to you by midnight Pacific time on June 30. All submissions will be entered into a drawing for a $50 Amazon.com gift card.

To whet your appetite for the survey, here is some background information on the proposed apps. We discussed in a previous blog post how our Cache Coherency TrekApp can generate test cases that stress every aspect of your SoC’s processors, memories, and buses or fabric. Since the ability to measure realistic performance is of high value even on SoCs that are not cache-coherent, we are considering releasing a dedicated Processor-Memory Workload TrekApp.

One of our most requested applications is a flexible packet generator for UVM testbenches. This was a surprise to us, since we figured that networking companies would have in-house solutions already. What we’ve heard is that many verification teams have multiple generators, most created for very specific tasks and protocols, that are hard to modify or support. So they see value in a turnkey commercial solution that would generate packets for Ethernet and other serial protocols. Sound useful? Then please check the box on our survey.

You may not know this, but the original roots of Breker’s graph-based approach were in CPU verification at AMD. Graphs were used to generate legal streams of x86 instructions to verify the processor design. Since most SoCs in recent years have used off-the-shelf processors we have not focused in this area much at Breker. However, a whole new generation of CPU designs is now underway as ARM architectural licensees develop customized processors. For these development teams, we could offer an ARM Instruction Stream Generation TrekApp.

Another trend is that SoCs have multiple domains for power, clocking, and security. There are formal techniques for verifying some aspects of the controllers, but formal can’t guarantee that your design still operates properly as power domains turn on and off, clock domains change speed, or programs try to access secure resources. We are considering building TrekApps that stress legal variations of power, clock, and security domains, overlaying realistic use cases with system-level scenarios. Please check the boxes of interest on our survey.

Finally, we are seeing that most customers are turning to commercial IP providers for standard interfaces and perhaps some computation engines (MPEG, GPU, etc.) as well. All complex IP blocks have register sets that must be programmed by one of the SoC’s processors to perform their operations. In the case of a custom block, we work with the customer to develop a scenario model that leverages any existing software drivers. For commercial IP, we could provide a TrekApp that already has all the information needed.

Note that the key defining aspect of all TrekApps is that no knowledge of graphs or graph-based scenario models is needed. TrekApps are pushbutton solutions containing pre-built scenario models. If any or all of our proposals could be valuable for your SoC projects, please fill out the survey by June 30. You’ll be doing us a great favor in helping to guide the evolution of our Trek product line, and you may win $50 in return. Thanks in advance, and please share any additional ideas for TrekApps on the survey or by commenting below.

Tom A.

The truth is out there … sometimes it’s in a blog.

Tags: ARM, Breker, cache coherency, clock domains, EDA, Ethernet, functional verification, graph, graph-based, IP, low power, PCIe, portable stimulus, scenario model, security, simulation, SoC verification, TrekApp, USB, use cases, uvm, VIP

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