The Importance of DVCon and Why Breker Will Be There

Most of the time when we blog about upcoming conferences, report live from an ongoing show, or summarize one that’s just finished, we see a significant spike in readership. Clearly our followers want to keep up with what’s happening in trade shows, conferences, and other industry events. It may also be the case that tighter travel budgets have reduced the ability to attend conferences in person, driving all the more interest in reading the news from the field. A few weeks ago, we discussed DesignCon and explained how it had evolved to include almost no verification content.

Next week is the annual Design and Verification Conference (DVCon) in San Jose, an event that we have covered in considerable detail in several popular posts in the past. As we have discussed, this conference has become the main way to keep up on what’s happening in the ever-changing world of functional verification. We encourage you to check out their Web site and the complete program. The topics include the UVM, SystemVerilog, SystemC, code generation, multi-language, mixed-signal, formal techniques, coverage metrics, and low-power verification.

Of course, DVCon wouldn’t be as important to Breker without the exhibition. The floor looks to be sold out once again, so you’ll be able to visit every major verification vendor without incurring the sore feat and long days of broader shows such as the Design Automation Conference (DAC). Breker will be in booth 905, decked out with a brand-new backdrop, new handouts, and a new demo. we always look forward to meeting old friends at this show as well as making new ones, so please be sure and stop by to see us.

Our theme this year is simple: “Portable Stimulus and Tests Available Now!” Two weeks ago we talked about the new Accellera Portable Stimulus Working Group and its charter to “develop the electronic industry’s first standard for portable test and stimulus.” We are actively participating in this group already and are committed to a leadership role in creating the new standard. But in the meantime, we want to be clear that we have a proven solution today providing both vertical reuse from IP to SoC and horizontal reuse across all verification platforms.

So we will be talking about Accellera, but we’ll also be presenting two of the biggest advancements in our verification solution since last year’s DVCon and DAC shows. First, our partnership with Carbon Design Systems has been working out very well. We have built multiple Carbon Performance Analysis Kits (CPAKs) that enable SoC teams to run our automatically generated multi-threaded tests on the accurate, efficient Carbon processor and system models. We produce a high level of traffic that stresses your SoC well enough for accurate performance verification.

If your design contains cache-coherent processors, and if it doesn’t already it probably will, our Cache Coherency TrekApp will also stress your caches and cache logic. We play tricks such as having two processors in different clusters access two halves of the same cache line to ensure that all your memory contents remain consistent. This TrekApp is only the first in a growing family that we will be glad to discuss with you. Each TrekApp is a pushbutton solution to a specific verification problem, requiring no knowledge of our underlying technology of graph-based scenario models.

The DVCon technical program runs from Monday, March 2 through Thursday, March 5. You can visit the exhibition floor Monday 5:00-7:00pm, Tuesday 2:30-6:00pm, and Wednesday 2:30-6:00pm. Finally, if you are an Accellera member, we encourage you to join the Portable Stimulus Working Group and attend the kickoff meeting on Thursday evening. All of these events take place next week in the DoubleTree hotel in San Jose. We hope to see you there!

Tom A.

The truth is out there … sometimes it’s in a blog.

Tags: Accellera, Breker, cache coherency, Carbon, CPAK, DesignCon, dvcon, EDA, functional verification, integration verification, IP, portable stimulus, standards, Trek, TrekApp, TrekSoC, verification IP, VIP

This entry was posted on Tuesday, February 24th, 2015 at 6:56 pm. You can follow any responses to this entry through the RSS 2.0 feed. You can leave a response, or trackback from your own site.